Searched refs:ADDR_TM_3D_TILED_THIN1 (Results 1 – 5 of 5) sorted by relevance
183 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1130 case ADDR_TM_3D_TILED_THIN1: in ComputeSurfaceMipLevelTileMode()1256 expTileMode = ADDR_TM_3D_TILED_THIN1; in HwlDegradeThickTileMode()1274 expTileMode = ADDR_TM_3D_TILED_THIN1; in HwlDegradeThickTileMode()1388 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2253 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()2513 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()3027 case ADDR_TM_3D_TILED_THIN1: // fall through in ComputeBankFromCoord()3049 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputeBankFromCoord()3122 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputePipeRotation()[all …]
799 tileMode == ADDR_TM_3D_TILED_THIN1 || in HwlComputeFmaskInfo()805 ADDR_ASSERT(m_tileTable[15].mode == ADDR_TM_3D_TILED_THIN1); in HwlComputeFmaskInfo()1070 tileMode = ADDR_TM_3D_TILED_THIN1; in HwlOverrideTileMode()1292 else if (tileMode == ADDR_TM_3D_TILED_THIN1 || tileMode == ADDR_TM_PRT_3D_TILED_THIN1) in HwlSetupTileInfo()1414 case ADDR_TM_3D_TILED_THIN1: in HwlSetupTileInfo()
797 case ADDR_TM_3D_TILED_THIN1: //fall through thin in ComputePipeFromCoord()3841 (tileConfig.mode == ADDR_TM_3D_TILED_THIN1) || in IsEquationSupported()
192 ADDR_TM_3D_TILED_THIN1 = 12, ///< Macro tiling w/ pipe rotation between slices enumerator
3801 tileMode = ADDR_TM_3D_TILED_THIN1; in DegradeLargeThickTile()