Searched refs:AMDGPU_TILING_SET (Results 1 – 4 of 4) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 893 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
894 tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b); in radv_amdgpu_winsys_bo_set_metadata()
895 tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max); in radv_amdgpu_winsys_bo_set_metadata()
896 tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
898 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, md->u.gfx9.dcc_independent_128b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
900 AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, md->u.gfx9.dcc_max_compressed_block_size); in radv_amdgpu_winsys_bo_set_metadata()
901 tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout); in radv_amdgpu_winsys_bo_set_metadata()
904 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
906 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
908 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */ in radv_amdgpu_winsys_bo_set_metadata()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.c | 78 #define AMDGPU_TILING_SET(field, value) \ macro
2672 *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.swizzle_mode); in ac_surface_get_bo_metadata()
2673 *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8); in ac_surface_get_bo_metadata()
2674 *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.color.display_dcc_pitch_max); in ac_surface_get_bo_metadata()
2676 AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.color.dcc.independent_64B_blocks); in ac_surface_get_bo_metadata()
2678 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.color.dcc.independent_128B_blocks); in ac_surface_get_bo_metadata()
2679 *tiling_flags |= AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, in ac_surface_get_bo_metadata()
2681 *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0); in ac_surface_get_bo_metadata()
2684 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ in ac_surface_get_bo_metadata()
2686 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ in ac_surface_get_bo_metadata()
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| /third_party/libdrm/include/drm/ |
| D | amdgpu_drm.h | 377 #define AMDGPU_TILING_SET(field, value) \ macro
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| /third_party/mesa3d/include/drm-uapi/ |
| D | amdgpu_drm.h | 381 #define AMDGPU_TILING_SET(field, value) \ macro
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