| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 36 ASR, enumerator
57 case AArch64_AM::ASR: return "asr"; in getShiftExtendName()
78 case 2: return AArch64_AM::ASR; in getShiftType()
106 case AArch64_AM::ASR: STEnc = 2; break; in getShifterImm()
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| /third_party/ltp/tools/sparse/sparse-src/ |
| D | opcode.def | 25 OPCODE(LSR, BADOP, BADOP, ASR, BADOP, 2, OPF_TARGET|OPF_BINOP)
26 OPCODE(ASR, BADOP, BADOP, LSR, BADOP, 2, OPF_TARGET|OPF_BINOP)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 40 ASR, ///< Arithmetic shift right. enumerator
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| D | AVRISelLowering.cpp | 259 NODE(ASR); in getTargetNodeName()
314 Opc8 = AVRISD::ASR; in LowerShifts()
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.h | 205 A_ALU2(ASR)
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| D | vc4_qpu_emit.c | 270 A(ASR), in vc4_generate_code_block()
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| D | vc4_qir.h | 694 QIR_ALU2(ASR) in QIR_ALU1()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.def | 98 X(ASR, "asr") \
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| D | IceTargetLoweringARM32.cpp | 2610 const bool ASR = Op == InstArithmetic::Ashr; in lowerInt64Arithmetic() local
2626 if (ASR) { in lowerInt64Arithmetic()
2634 if (ASR) { in lowerInt64Arithmetic()
2655 if (ASR) { in lowerInt64Arithmetic()
2708 if (ASR) { in lowerInt64Arithmetic()
3758 OperandARM32::ASR, ShiftAmt)); in lowerCast()
5454 NewShiftKind = OperandARM32::ASR; in matchShiftedOffsetReg()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 206 EMIT2(ASR)
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| D | brw_vec4_builder.h | 399 ALU2(ASR) in ALU2_ACC()
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| D | brw_fs_builder.h | 607 ALU2(ASR) in ALU3()
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| D | brw_vec4_nir.cpp | 858 bld.ASR(dst_reg(temp), src, brw_imm_d(31)); in emit_find_msb_using_lzd()
1828 emit(ASR(dst, op[0], op[1])); in nir_emit_alu()
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| D | brw_vec4_visitor.cpp | 177 ALU2(ASR) in ALU1()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | FunctionComparator.cpp | 665 unsigned int ASR = GEPR->getPointerAddressSpace(); in cmpGEPs() local
667 if (int Res = cmpNumbers(ASL, ASR)) in cmpGEPs()
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 56 asr { yylval.integer = BRW_OPCODE_ASR; return ASR; }
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| D | i965_gram.y | 385 %token <integer> ADD ADD3 ADDC AND ASR AVG
824 | ASR
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| /third_party/ltp/tools/sparse/sparse-src/Documentation/release-notes/ |
| D | v0.6.0.rst | 103 * simplify ZEXT + ASR into ZEXT + LSR
749 * big-shift: mark out-of-range OP_{ASR,LSR,SHL} as tainted
796 * shift: simplify ASR(LSR(x,N),N')
797 * shift: avoid simplification of ASR(LSR(x,0),N)
798 * shift: simplify ASR(ZEXT(X, N), C)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 454 ASR, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 1949 cmp(hi, Operand(lo, ASR, kBitsPerWord - 1)); in ComputeRange()
2483 mov(rd, Operand(rm, ASR, shift), cond);
2495 movs(rd, Operand(rm, ASR, shift), cond); in Asrs()
2501 mov(rd, Operand(rm, ASR, rs), cond);
3402 add(base, array, Operand(index, ASR, 1)); in ElementAddressForRegIndex()
3409 return Address(array, index, ASR, 1); in ElementAddressForRegIndex()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 50 def CheckShiftASR : CheckImmOperand_s<3, "AArch64_AM::ASR">;
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| D | AArch64FastISel.cpp | 1284 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break; in emitAddSub()
3771 AArch64_AM::ASR, 31, /*WantResult=*/false); in fastLowerIntrinsicCall()
3781 AArch64_AM::ASR, 63, /*WantResult=*/false); in fastLowerIntrinsicCall()
4983 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2); in selectSDiv()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 361 (add Y, (sequence "ASR%u", 1, 31))>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1209 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1304 ST == AArch64_AM::ASR) && getShiftExtendAmount() < width; in isArithmeticShifter()
1315 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
2747 .Case("asr", AArch64_AM::ASR) in tryParseOptionalShiftExtend()
2770 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1329 VIR_A_ALU2(ASR) in VIR_A_ALU2()
|