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Searched refs:AllocateReg (Results 1 – 21 of 21) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc176 if (unsigned Reg = State.AllocateReg(RegList1)) {
188 if (unsigned Reg = State.AllocateReg(RegList2)) {
200 if (unsigned Reg = State.AllocateReg(RegList3)) {
212 if (unsigned Reg = State.AllocateReg(RegList4)) {
234 if (unsigned Reg = State.AllocateReg(RegList6)) {
247 if (unsigned Reg = State.AllocateReg(RegList7)) {
260 if (unsigned Reg = State.AllocateReg(RegList8)) {
268 if (unsigned Reg = State.AllocateReg(X86::K1)) {
396 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
408 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc57 if (unsigned Reg = State.AllocateReg(ARM::R12)) {
85 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
94 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
143 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
155 if (unsigned Reg = State.AllocateReg(RegList3)) {
255 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
264 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
280 if (unsigned Reg = State.AllocateReg(RegList1)) {
290 if (unsigned Reg = State.AllocateReg(RegList2)) {
300 if (unsigned Reg = State.AllocateReg(RegList3)) {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenCallingConv.inc52 if (unsigned Reg = State.AllocateReg(RegList1)) {
70 if (unsigned Reg = State.AllocateReg(RegList2)) {
82 if (unsigned Reg = State.AllocateReg(RegList3)) {
163 if (unsigned Reg = State.AllocateReg(PPC::R11)) {
173 if (unsigned Reg = State.AllocateReg(RegList1)) {
192 if (unsigned Reg = State.AllocateReg(RegList2)) {
211 if (unsigned Reg = State.AllocateReg(RegList3)) {
362 if (unsigned Reg = State.AllocateReg(RegList1)) {
373 if (unsigned Reg = State.AllocateReg(RegList2)) {
421 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc95 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
106 if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
119 if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
127 if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
136 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
161 if (unsigned Reg = State.AllocateReg(RegList3)) {
188 if (unsigned Reg = State.AllocateReg(RegList4)) {
221 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
235 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
260 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.cpp27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
42 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
72 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
76 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
95 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
122 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
209 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
263 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
DARMISelLowering.cpp2495 unsigned Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2502 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2515 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()
2532 State->AllocateReg(GPRArgRegs); in HandleByVal()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
118 unsigned Reg = State.AllocateReg(HiRegList); in CC_PPC32_SPE_CustomSplitFP64()
127 unsigned T = State.AllocateReg(LoRegList[i]); in CC_PPC32_SPE_CustomSplitFP64()
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in CC_PPC32_SPE_RetF64()
DPPCISelLowering.cpp6900 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
6920 if (unsigned Reg = State.AllocateReg(FPR)) in CC_AIX()
6930 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.cpp53 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
104 unsigned AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister()
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); in CC_X86_64_VectorCall()
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); in CC_X86_64_VectorCall()
160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_64_VectorCall()
211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_32_VectorCall()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenCallingConv.inc99 if (unsigned Reg = State.AllocateReg(RegList1)) {
158 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
171 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
184 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
215 if (unsigned Reg = State.AllocateReg(RegList1)) {
225 if (unsigned Reg = State.AllocateReg(RegList2)) {
252 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
302 if (unsigned Reg = State.AllocateReg(RegList1)) {
313 if (unsigned Reg = State.AllocateReg(RegList2)) {
396 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp394 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
400 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
406 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
417 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
423 CCInfo.AllocateReg(DispatchIDReg); in allocateHSAUserSGPRs()
429 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()
602 CCInfo.AllocateReg(ImplicitBufferPtrReg); in lowerFormalArguments()
678 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
679 CCInfo.AllocateReg(AMDGPU::VGPR1); in lowerFormalArguments()
721 CCInfo.AllocateReg(Info->getScratchRSrcReg()); in lowerFormalArguments()
[all …]
DSIISelLowering.cpp1634 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1642 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1650 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1675 Reg = CCInfo.AllocateReg(Reg); in allocateVGPR32Input()
1693 Reg = CCInfo.AllocateReg(Reg); in allocateSGPR32InputImpl()
1774 CCInfo.AllocateReg(ImplicitBufferPtrReg); in allocateHSAUserSGPRs()
1781 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
1787 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
1793 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
1799 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DCallingConvLower.h354 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
361 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZCallingConv.h110 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs); in CC_SystemZ_I128Indirect()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp1427 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
1444 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
1525 State.AllocateReg(ArgGPRs); in CC_RISCV()
1544 Register Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
1552 if (!State.AllocateReg(ArgGPRs)) in CC_RISCV()
1588 Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s); in CC_RISCV()
1590 Reg = State.AllocateReg(ArgFPR64s, ArgFPR32s); in CC_RISCV()
1592 Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
1831 if (unsigned Reg = State.AllocateReg(GPRList)) { in CC_RISCV_FastCC()
1843 if (unsigned Reg = State.AllocateReg(FPR32List)) { in CC_RISCV_FastCC()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.cpp147 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2914 Reg = State.AllocateReg(FloatVectorIntRegs); in CC_MipsO32()
2916 State.AllocateReg(Mips::A1); in CC_MipsO32()
2918 State.AllocateReg(Mips::A3); in CC_MipsO32()
2922 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2926 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2930 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2935 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2937 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2938 State.AllocateReg(IntRegs); in CC_MipsO32()
2943 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp530 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
538 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp62 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
73 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
91 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
97 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRISelLowering.cpp982 unsigned Reg = CCInfo.AllocateReg( in analyzeStandardArguments()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp144 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()