| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.cpp | 36 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
40 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
61 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
65 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
86 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
91 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
[all …]
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| D | PPCFastISel.cpp | 189 SmallVectorImpl<unsigned> &ArgRegs,
1375 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument
1432 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1599 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local
1604 ArgRegs.reserve(NumArgs); in fastLowerCall()
1630 ArgRegs.push_back(Arg); in fastLowerCall()
1639 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 501 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in lowerFormalArguments() local
502 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in lowerFormalArguments()
506 if (ArgRegs.size() == Idx) in lowerFormalArguments()
511 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
518 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
519 MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); in lowerFormalArguments()
522 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); in lowerFormalArguments()
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| D | MipsISelLowering.cpp | 4372 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
4383 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4432 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4456 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local
4457 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
4468 if (ArgRegs.size() == Idx) in writeVarArgRegs()
4473 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
4485 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
4487 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 521 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
524 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
525 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCallArguments()
532 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, in LowerCallArguments()
536 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { in LowerCallArguments()
539 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCallArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 222 SmallVectorImpl<Register> &ArgRegs,
1888 SmallVectorImpl<Register> &ArgRegs, in ProcessCallArgs() argument
1955 Register Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2226 SmallVector<Register, 8> ArgRegs; in ARMEmitLibcall() local
2230 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2245 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2253 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2334 SmallVector<Register, 8> ArgRegs; in SelectCall() local
2339 ArgRegs.reserve(arg_size); in SelectCall()
2378 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 333 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 34 ArrayRef<ArrayRef<Register>> ArgRegs, in lowerCall() argument
46 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, in lowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1346 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1350 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1351 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1355 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1365 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1956 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); in LowerFormalArguments() local
1957 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
1970 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
1974 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
1993 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
1996 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 135 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local
139 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_SkipOdd()
140 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_SkipOdd()
144 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 536 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3250 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local
3295 ArgRegs.push_back(ResultReg); in fastLowerCall()
3327 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
|