Searched refs:BRW_OPCODE_ROR (Results 1 – 8 of 8) sorted by relevance
| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_eu.c | 624 { BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
625 { BRW_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) },
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| D | brw_eu_defines.h | 193 BRW_OPCODE_ROR, /**< Gfx11+ */ enumerator
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| D | brw_shader.cpp | 969 case BRW_OPCODE_ROR: in can_do_source_mods()
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| D | brw_ir_performance.cpp | 325 case BRW_OPCODE_ROR: in instruction_desc()
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| D | brw_fs_generator.cpp | 2004 case BRW_OPCODE_ROR: in generate_code()
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| D | brw_fs.cpp | 4823 case BRW_OPCODE_ROR: in get_lowered_simd_width()
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 118 ror { yylval.integer = BRW_OPCODE_ROR; return ROR; }
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| D | i965_gram.y | 205 case BRW_OPCODE_ROR: in i965_asm_binary_instruction()
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