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Searched refs:COND (Results 1 – 25 of 88) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_asm.c75 COND(inst->sat, VIV_ISA_WORD_0_SAT) | in etna_assemble()
76 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) | in etna_assemble()
83 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) | in etna_assemble()
85 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) | in etna_assemble()
87 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) | in etna_assemble()
88 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS); in etna_assemble()
91 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) | in etna_assemble()
93 COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) | in etna_assemble()
95 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) | in etna_assemble()
96 COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) | in etna_assemble()
[all …]
Detnaviv_rasterizer.c53 COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) | in etna_rasterizer_state_create()
54 COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) | in etna_rasterizer_state_create()
55 … COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE); in etna_rasterizer_state_create()
60 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE); in etna_rasterizer_state_create()
64 COND(!so->flatshade_first, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST) | in etna_rasterizer_state_create()
65 COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER); in etna_rasterizer_state_create()
Detnaviv_texture_desc.c113 COND(ss->lod_bias != 0.0, VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE); in etna_create_sampler_state_desc()
114 cs->SAMP_ANISOTROPY = COND(ansio, etna_log2_fixp88(ss->max_anisotropy)); in etna_create_sampler_state_desc()
188 DESC_SET(CONFIG0, COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format)) in etna_create_sampler_view_desc()
190 COND(res->layout == ETNA_LAYOUT_LINEAR && !util_format_is_compressed(so->format), in etna_create_sampler_view_desc()
192 DESC_SET(CONFIG1, COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) | in etna_create_sampler_view_desc()
193 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) | in etna_create_sampler_view_desc()
194 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) | in etna_create_sampler_view_desc()
197 COND(sint && desc->channel[0].size == 8, TE_SAMPLER_CONFIG2_SIGNED_INT8) | in etna_create_sampler_view_desc()
198 COND(sint && desc->channel[0].size == 16, TE_SAMPLER_CONFIG2_SIGNED_INT16)); in etna_create_sampler_view_desc()
203 DESC_SET(ASTC0, COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) | in etna_create_sampler_view_desc()
[all …]
Detnaviv_texture_state.c105 VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(COND(ansio, etna_log2_fixp55(ss->max_anisotropy))); in etna_create_sampler_state_state()
114 COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP) : 0; in etna_create_sampler_state_state()
117 COND(ss->lod_bias != 0.0 && mipmap, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) | in etna_create_sampler_state_state()
139 COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) | in etna_create_sampler_state_state()
194 COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format)); in etna_create_sampler_view_state()
234 sv->config1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) | in etna_create_sampler_view_state()
235 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) | in etna_create_sampler_view_state()
236 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) | in etna_create_sampler_view_state()
238 sv->astc0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) | in etna_create_sampler_view_state()
239 COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB) | in etna_create_sampler_view_state()
[all …]
Detnaviv_rs.c78 unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2); in etna_compile_rs_state()
79 unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2); in etna_compile_rs_state()
97 COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) | in etna_compile_rs_state()
98 COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) | in etna_compile_rs_state()
99 COND(src_tiled, VIVS_RS_CONFIG_SOURCE_TILED) | in etna_compile_rs_state()
101 COND(dst_tiled, VIVS_RS_CONFIG_DEST_TILED) | in etna_compile_rs_state()
102 COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) | in etna_compile_rs_state()
103 COND(rs->flip, VIVS_RS_CONFIG_FLIP); in etna_compile_rs_state()
106 COND(src_super, VIVS_RS_SOURCE_STRIDE_TILING) | in etna_compile_rs_state()
107 COND(src_multi, VIVS_RS_SOURCE_STRIDE_MULTI); in etna_compile_rs_state()
[all …]
Detnaviv_state.c171 COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED); in etna_set_framebuffer_state()
173 cs->PE_COLOR_FORMAT |= COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); in etna_set_framebuffer_state()
233 cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0); in etna_set_framebuffer_state()
268 COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) | in etna_set_framebuffer_state()
302 COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8, in etna_set_framebuffer_state()
307 ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP); in etna_set_framebuffer_state()
583 COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) | in etna_vertex_elements_state_create()
598 COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) | in etna_vertex_elements_state_create()
758 COND(zsa->z_write_enabled, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) | in etna_update_zsa()
759 COND(early_z_test, VIVS_PE_DEPTH_CONFIG_EARLY_Z) | in etna_update_zsa()
[all …]
/third_party/flutter/skia/include/gpu/
DGrConfig.h133 #define GR_ALWAYSASSERT(COND) \ argument
135 if (!(COND)) { \
136 SkDebugf("%s %s failed\n", GR_FILE_AND_LINE_STR, #COND); \
147 #define GR_DEBUGASSERT(COND) GR_ALWAYSASSERT(COND) argument
149 #define GR_DEBUGASSERT(COND) argument
156 #define GrAlwaysAssert(COND) GR_ALWAYSASSERT(COND) argument
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_program.c253 COND(s[VS].v && s[VS].v->has_ssbo, A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE) | in fd4_program_emit()
254 COND(s[VS].v, A4XX_HLSQ_VS_CONTROL_REG_ENABLED) | in fd4_program_emit()
260 COND(s[FS].v && s[FS].v->has_ssbo, A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE) | in fd4_program_emit()
261 COND(s[FS].v, A4XX_HLSQ_FS_CONTROL_REG_ENABLED) | in fd4_program_emit()
267 COND(s[HS].v && s[HS].v->has_ssbo, A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE) | in fd4_program_emit()
273 COND(s[DS].v && s[DS].v->has_ssbo, A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE) | in fd4_program_emit()
279 COND(s[GS].v && s[GS].v->has_ssbo, A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE) | in fd4_program_emit()
286 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS)); in fd4_program_emit()
290 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) | in fd4_program_emit()
291 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) | in fd4_program_emit()
[all …]
Dfd4_emit.c577 COND(elem->instance_divisor, in fd4_emit_vertex_bufs()
579 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT)); in fd4_emit_vertex_bufs()
594 COND(isint, A4XX_VFD_DECODE_INSTR_INT) | in fd4_emit_vertex_bufs()
595 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd4_emit_vertex_bufs()
615 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT)); in fd4_emit_vertex_bufs()
628 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd4_emit_vertex_bufs()
718 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) | in fd4_emit_state()
719 COND(latez, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) | in fd4_emit_state()
720 COND(fragz && fp->fragcoord_compmask != 0, in fd4_emit_state()
728 COND(latez, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) | in fd4_emit_state()
[all …]
Dfd4_blend.c99 COND(cso->logicop_enable, A4XX_RB_MRT_CONTROL_ROP_ENABLE) | in fd4_blend_state_create()
121 COND(cso->independent_blend_enable, A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND); in fd4_blend_state_create()
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_program.c133 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) | in emit_stream_out()
134 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) | in emit_stream_out()
135 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) | in emit_stream_out()
136 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3)); in emit_stream_out()
301 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED)); in fd5_program_emit()
304 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED)); in fd5_program_emit()
307 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED)); in fd5_program_emit()
310 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED)); in fd5_program_emit()
313 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED)); in fd5_program_emit()
320 COND(s[VS].v && s[VS].v->has_ssbo, in fd5_program_emit()
[all …]
Dfd5_emit.h134 OUT_RING(ring, COND(mode == GMEM, CP_SET_RENDER_MODE_3_GMEM_ENABLE) | in fd5_set_render_mode()
135 COND(mode == BINNING, CP_SET_RENDER_MODE_3_VSC_ENABLE)); in fd5_set_render_mode()
178 COND(binning, A5XX_RB_RENDER_CNTL_BINNING_PASS) | in fd5_emit_render_cntl()
179 COND(binning, A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE) | in fd5_emit_render_cntl()
180 COND(samples_passed, A5XX_RB_RENDER_CNTL_SAMPLES_PASSED) | in fd5_emit_render_cntl()
181 COND(!blit, 0x8)); in fd5_emit_render_cntl()
185 COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) | in fd5_emit_render_cntl()
186 COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED)); in fd5_emit_render_cntl()
Dfd5_blend.c102 COND(cso->logicop_enable, A5XX_RB_MRT_CONTROL_ROP_ENABLE) | in fd5_blend_state_create()
126 COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) | in fd5_blend_state_create()
127 COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND); in fd5_blend_state_create()
131 COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE); in fd5_blend_state_create()
Dfd5_gmem.c104 COND(gmem, in emit_mrt()
106 COND(srgb, A5XX_RB_MRT_BUF_INFO_COLOR_SRGB)); in emit_mrt()
118 COND(sint, A5XX_SP_FS_MRT_REG_COLOR_SINT) | in emit_mrt()
119 COND(uint, A5XX_SP_FS_MRT_REG_COLOR_UINT) | in emit_mrt()
120 COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB)); in emit_mrt()
245 COND(samples == MSAA_ONE, in emit_msaa()
252 COND(samples == MSAA_ONE, A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE)); in emit_msaa()
257 COND(samples == MSAA_ONE, in emit_msaa()
657 COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED)); in emit_gmem2mem_surf()
668 OUT_RING(ring, COND(msaa_resolve, A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE)); in emit_gmem2mem_surf()
Dfd5_texture.c95 COND(miplinear, A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) | in fd5_sampler_state_create()
104 COND(!cso->seamless_cube_map, A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF) | in fd5_sampler_state_create()
105 COND(!cso->normalized_coords, A5XX_TEX_SAMP_1_UNNORM_COORDS); in fd5_sampler_state_create()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_program.c139 COND(so->pvtmem_per_wave, in fd6_emit_shader()
253 COND(strmout->stride[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) | in setup_stream_out()
254 COND(strmout->stride[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) | in setup_stream_out()
255 COND(strmout->stride[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) | in setup_stream_out()
256 COND(strmout->stride[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1))); in setup_stream_out()
270 OUT_RING(ring, COND(first, A6XX_VPC_SO_CNTL_RESET) | in setup_stream_out()
305 OUT_RING(ring, COND(state->hs, in setup_config_stateobj()
308 OUT_RING(ring, COND(state->ds, in setup_config_stateobj()
311 OUT_RING(ring, COND(state->gs, in setup_config_stateobj()
319 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) | in setup_config_stateobj()
[all …]
Dfd6_blitter.c268 COND(color, A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR) | in emit_blit_setup()
269 COND(scissor_enable, A6XX_RB_2D_BLIT_CNTL_SCISSOR); in emit_blit_setup()
288 COND(util_format_is_pure_sint(pfmt), A6XX_SP_2D_DST_FORMAT_SINT) | in emit_blit_setup()
289 COND(util_format_is_pure_uint(pfmt), A6XX_SP_2D_DST_FORMAT_UINT) | in emit_blit_setup()
290 COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) | in emit_blit_setup()
551 COND(util_format_is_srgb(pfmt), A6XX_RB_2D_DST_INFO_SRGB) | in emit_blit_dst()
552 COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS)); in emit_blit_dst()
599 COND(samples > MSAA_ONE && !sample_0, in emit_blit_src()
601 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) | in emit_blit_src()
602 COND(util_format_is_srgb(info->src.format), in emit_blit_src()
[all …]
/third_party/mesa3d/src/freedreno/fdl/
Dfd6_view.c159 #define COND(bool, val) ((bool) ? (val) : 0) macro
246 COND(util_format_is_srgb(args->format), A6XX_TEX_CONST_0_SRGB) | in fdl6_view_init()
332 COND(ubwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) | in fdl6_view_init()
333 COND(util_format_is_srgb(args->format), A6XX_SP_PS_2D_SRC_INFO_SRGB) | in fdl6_view_init()
335 COND(samples_average, A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) | in fdl6_view_init()
412 COND(util_format_is_pure_sint(args->format), A6XX_SP_FS_MRT_REG_COLOR_SINT) | in fdl6_view_init()
413 COND(util_format_is_pure_uint(args->format), A6XX_SP_FS_MRT_REG_COLOR_UINT); in fdl6_view_init()
419 COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS) | in fdl6_view_init()
420 COND(util_format_is_srgb(args->format), A6XX_RB_2D_DST_INFO_SRGB); in fdl6_view_init()
427 COND(ubwc_enabled, A6XX_RB_BLIT_DST_INFO_FLAGS); in fdl6_view_init()
[all …]
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_program.c225 COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) | in fd3_program_emit()
236 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) | in fd3_program_emit()
307 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) | in fd3_program_emit()
313 COND(fp->need_pixlod, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) | in fd3_program_emit()
329 OUT_RING(ring, COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) | in fd3_program_emit()
337 COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION); in fd3_program_emit()
342 COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) | in fd3_program_emit()
343 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT); in fd3_program_emit()
351 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE)); in fd3_program_emit()
416 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE)); in fd3_program_emit()
Dfd3_emit.c432 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) | in fd3_emit_vertex_bufs()
434 COND(elem->instance_divisor, in fd3_emit_vertex_bufs()
449 COND(isint, A3XX_VFD_DECODE_INSTR_INT) | in fd3_emit_vertex_bufs()
450 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd3_emit_vertex_bufs()
470 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) | in fd3_emit_vertex_bufs()
483 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd3_emit_vertex_bufs()
527 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS); in fd3_emit_state()
528 val |= COND(fp->fragcoord_compmask != 0, in fd3_emit_state()
530 val |= COND(ctx->rasterizer->rasterizer_discard, in fd3_emit_state()
612 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE); in fd3_emit_state()
[all …]
Dfd3_texture.c95 COND(!cso->normalized_coords, A3XX_TEX_SAMP_0_UNNORM_COORDS) | in fd3_sampler_state_create()
96 COND(!cso->seamless_cube_map, A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF) | in fd3_sampler_state_create()
97 COND(miplinear, A3XX_TEX_SAMP_0_MIPFILTER_LINEAR) | in fd3_sampler_state_create()
/third_party/skia/gm/
Dpreservefillrule.cpp22 #define ERR_MSG_ASSERT(COND) \ argument
24 if (!(COND)) { \
26 __LINE__, #COND); \
/third_party/flutter/skia/gm/
Dpreservefillrule.cpp22 #define ERR_MSG_ASSERT(COND) \ argument
24 if (!(COND)) { \
26 __LINE__, #COND); \
/third_party/libdrm/
Dlibdrm_macros.h40 #define STATIC_ASSERT(COND) \ argument
42 (void) sizeof(char [1 - 2*!(COND)]); \
/third_party/jerryscript/jerry-ext/include/jerryscript-ext/
Dhandle-scope.h34 #define STATIC_ASSERT(COND,MSG) typedef char static_assertion_##MSG[(COND)?1:-1] argument

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