| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 84 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
444 case ISD::CopyFromReg: in SUSchedulingCost()
549 case ISD::CopyFromReg: in initNumRegDefsLeft()
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| D | StatepointLowering.cpp | 342 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
982 SDValue CopyFromReg = getCopyFromRegs(I, RetTy); in visitGCResult() local
984 assert(CopyFromReg.getNode()); in visitGCResult()
985 setValue(&CI, CopyFromReg); in visitGCResult()
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| D | ScheduleDAGRRList.cpp | 323 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
711 case ISD::CopyFromReg: in EmitNode()
1279 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2271 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2362 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2433 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2450 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3001 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| D | InstrEmitter.cpp | 341 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
947 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1018 case ISD::CopyFromReg: { in EmitSpecialNode()
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| D | ScheduleDAGSDNodes.cpp | 122 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
547 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| D | ScheduleDAGFast.cpp | 428 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
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| D | SelectionDAGDumper.cpp | 171 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
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| D | SelectionDAGBuilder.cpp | 5524 case ISD::CopyFromReg: { in getUnderlyingArgRegs()
8846 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
9425 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
9929 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
9938 if (Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
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| D | SelectionDAGISel.cpp | 2797 case ISD::CopyFromReg: in SelectCodeCommon()
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| D | DAGCombiner.cpp | 1859 case ISD::CopyFromReg: in visitTokenFactor()
7345 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
20969 case ISD::CopyFromReg: in GatherAllAliases()
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| D | TargetLowering.cpp | 94 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 250 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
300 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
303 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
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| D | X86InstrCompiler.td | 1344 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1347 // 32 bits, they're probably just qualifying a CopyFromReg.
1351 N->getOpcode() != ISD::CopyFromReg &&
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| D | X86ISelDAGToDAG.cpp | 392 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
2107 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
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| D | X86ISelLowering.cpp | 4397 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
22337 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){ in LowerSELECT()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 176 CopyFromReg, enumerator
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| D | SelectionDAG.h | 732 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
742 return getNode(ISD::CopyFromReg, dl, VTs,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 294 Opc != ISD::CopyFromReg; in isDef32()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 388 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
394 N->getOpcode() != ISD::CopyFromReg;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 10864 assert(N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
10871 } while (N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
10879 case ISD::CopyFromReg: in isSDNodeSourceOfDivergence()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 3132 if (Ptr.getOpcode() == ISD::CopyFromReg && in Select()
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| D | ARMISelLowering.cpp | 2549 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
5731 if (Op.getOpcode() != ISD::CopyFromReg || in ExpandBITCAST()
5740 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops); in ExpandBITCAST()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 4225 return AddrOp.getOpcode() == ISD::CopyFromReg; in isOffsetMultipleOf()
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