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Searched refs:DefIdx (Results 1 – 25 of 42) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrItineraries.h181 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
185 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
187 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
195 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
202 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
207 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
217 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
DMCSubtargetInfo.h170 unsigned DefIdx) const { in getWriteLatencyEntry() argument
171 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
174 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetSchedule.cpp158 unsigned DefIdx = 0; in findDefIdx() local
162 ++DefIdx; in findDefIdx()
164 return DefIdx; in findDefIdx()
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
222 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
DTargetInstrInfo.cpp1037 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1047 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1049 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1111 unsigned DefIdx) const { in hasLowDefLatency()
1117 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1189 unsigned DefIdx, in getOperandLatency() argument
1194 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1214 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1220 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1224 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
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DPeepholeOptimizer.cpp370 unsigned DefIdx = 0; member in __anon4ac18f120111::ValueTracker
424 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1818 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1839 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1883 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1906 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1927 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1940 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
1956 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
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DLiveRangeCalc.cpp67 SlotIndex DefIdx = in createDeadDef() local
71 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
199 unsigned DefIdx; in extendToUses() local
202 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
205 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
DMachineVerifier.cpp269 SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1672 unsigned DefIdx; in visitMachineOperand() local
1674 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
1675 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
1892 unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit, in checkLivenessAtDef() argument
1894 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
1896 if (VNI->def != DefIdx) { in checkLivenessAtDef()
1903 report_context(DefIdx); in checkLivenessAtDef()
1911 report_context(DefIdx); in checkLivenessAtDef()
1915 LiveQueryResult LRQ = LR.Query(DefIdx); in checkLivenessAtDef()
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DLiveRangeEdit.cpp149 SlotIndex DefIdx; in canRematerializeAt() local
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
158 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
DMachineInstr.cpp281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
282 if (DefIdx != -1) in addOperand()
283 tieOperands(DefIdx, OpNo); in addOperand()
846 unsigned DefIdx; in getRegClassConstraint() local
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
848 OpIdx = DefIdx; in getRegClassConstraint()
1050 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1051 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1058 if (DefIdx < TiedMax) in tieOperands()
1059 UseMO.TiedTo = DefIdx + 1; in tieOperands()
DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
DTargetRegisterInfo.cpp352 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
355 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h59 const MachineInstr &MI, unsigned DefIdx,
72 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
88 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
318 const MachineInstr &DefMI, unsigned DefIdx,
322 SDNode *DefNode, unsigned DefIdx,
352 unsigned DefIdx, unsigned DefAlign) const;
356 unsigned DefIdx, unsigned DefAlign) const;
367 unsigned DefIdx, unsigned DefAlign,
372 const MachineInstr &DefMI, unsigned DefIdx,
389 const MachineInstr &DefMI, unsigned DefIdx,
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DARMBaseInstrInfo.cpp3746 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3747 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3750 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3803 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3804 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3807 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3906 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3912 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3913 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3922 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCSchedule.cpp43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
44 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCVSXSwapRemoval.cpp620 int DefIdx = SwapMap[DefMI]; in formWebs() local
621 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
625 SwapVector[DefIdx].VSEId, in formWebs()
701 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
703 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
704 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
710 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
777 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
778 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
DPPCInstrInfo.h213 const MachineInstr &DefMI, unsigned DefIdx,
217 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
219 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
225 unsigned DefIdx) const override { in hasLowDefLatency() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h327 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
328 ++j, ++DefIdx) in tryCombineMerges()
329 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineMerges()
363 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
365 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineMerges()
369 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineMerges()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h495 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
513 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
533 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1145 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1159 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1173 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1453 SDNode *DefNode, unsigned DefIdx,
1465 const MachineInstr &DefMI, unsigned DefIdx,
1498 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1508 unsigned DefIdx) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
218 DefIdx != DefEnd; ++DefIdx) { in getLatency()
221 DefIdx); in getLatency()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp571 DefIdx = 0; in InitNodeNumDefs()
577 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
585 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
586 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
588 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
589 ++DefIdx; in Advance()
651 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
655 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
DScheduleDAGSDNodes.h141 unsigned DefIdx; variable
160 return DefIdx-1; in GetIdx()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp204 unsigned DefIdx = 0; in tryInlineAsm() local
208 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in tryInlineAsm()
209 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
295 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in tryInlineAsm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp150 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands() local
151 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) in constrainSelectedInstRegOperands()
152 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp424 int DefIdx = -1; in restoreLatency() local
428 DefIdx = OpNum; in restoreLatency()
430 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
437 DefIdx, *DstI, OpNum)); in restoreLatency()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp536 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
538 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
539 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()

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