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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrSystem.td25 let hasSideEffects = 1, Defs = [CC] in {
31 let Uses = [R2L], Defs = [R2L] in
119 let hasSideEffects = 1, Defs = [CC] in
123 let hasSideEffects = 1, Defs = [CC] in
139 let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in
143 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
161 let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in
169 let hasSideEffects = 1, Defs = [CC] in {
175 let hasSideEffects = 1, Defs = [CC] in
179 let hasSideEffects = 1, Defs = [CC] in {
[all …]
DSystemZInstrHFP.td21 let Defs = [CC] in {
60 let Defs = [CC] in {
71 let Defs = [CC] in {
77 let Defs = [CC] in {
88 let Defs = [CC] in {
95 let Defs = [CC] in {
102 let Defs = [CC] in {
131 let Defs = [CC] in {
142 let Defs = [CC] in {
152 let Defs = [CC] in {
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DSystemZInstrDFP.td22 let Uses = [FPC], Defs = [CC] in {
66 let Uses = [FPC], Defs = [CC] in {
78 let Uses = [FPC], Defs = [CC] in {
116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in
145 let Uses = [FPC], Defs = [CC] in {
157 let Uses = [FPC], Defs = [CC] in {
216 let Uses = [FPC], Defs = [CC] in {
222 let Uses = [FPC], Defs = [CC] in {
228 let Defs = [CC] in {
234 let Defs = [CC] in {
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DSystemZInstrInfo.td110 let Defs = [CC] in {
134 let Defs = [CC] in {
168 let Defs = [CC] in {
183 let Defs = [CC] in {
250 let isCall = 1, Defs = [CC] in {
258 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in {
267 let isCall = 1, Defs = [R14D, CC] in {
367 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
413 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
471 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFormMemoryClauses.cpp67 bool canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
69 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
70 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
209 RegUse &Defs, RegUse &Uses) const { in canBundle() argument
226 RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
265 RegUse &Defs, RegUse &Uses) const { in collectRegUses() argument
276 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
293 RegUse &Defs, RegUse &Uses, in processRegUses() argument
295 if (!canBundle(MI, Defs, Uses)) in processRegUses()
301 collectRegUses(MI, Defs, Uses); in processRegUses()
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DSOPInstructions.td157 let Defs = [SCC] in {
167 } // End Defs = [SCC]
189 let Defs = [SCC] in {
198 } // End Defs = [SCC]
251 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
262 } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]
279 let Defs = [SCC] in {
281 } // End Defs = [SCC]
287 let Defs = [M0];
292 let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp100 BitVector Defs, Uses; member
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
165 expandReg(*R++, Defs); in getDefsUses()
175 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
184 BitVector Defs(NR), Uses(NR); in buildMaps() local
189 Defs.reset(); in buildMaps()
191 getDefsUses(MI, Defs, Uses); in buildMaps()
192 DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Uses))); in buildMaps()
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DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
182 Defs = [PC, R31, R6, R7, P0] in
219 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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DHexagonExpandCondsets.cpp222 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
391 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs, in updateDeadsInRange()
393 for (MachineBasicBlock *D : Defs) in updateDeadsInRange()
401 if (Defs.count(B)) in updateDeadsInRange()
414 SetVector<MachineBasicBlock*> Defs; in updateDeadsInRange() local
420 Defs.insert(DefI->getParent()); in updateDeadsInRange()
455 if (Dominate(Defs, BB)) in updateDeadsInRange()
794 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, in canMoveOver() argument
809 if (isRefInMap(RR, Defs, Exec_Then)) in canMoveOver()
968 ReferenceMap Uses, Defs; in predicate() local
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DHexagonBitSimplify.cpp201 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
271 RegisterSet Defs; in INITIALIZE_PASS_DEPENDENCY() local
273 getInstrDefs(I, Defs); in INITIALIZE_PASS_DEPENDENCY()
275 NewAVs.insert(Defs); in INITIALIZE_PASS_DEPENDENCY()
290 RegisterSet &Defs) { in getInstrDefs() argument
297 Defs.insert(R); in getInstrDefs()
1461 RegisterSet Defs; in processBlock() local
1466 Defs.clear(); in processBlock()
1467 HBS::getInstrDefs(*I, Defs); in processBlock()
1468 if (Defs.count() != 1) in processBlock()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td98 class Defs<list<Register> Regs> {
99 list<Register> Defs = Regs;
561 Defs<[DSPOutFlag20]>;
565 IsCommutable, Defs<[DSPOutFlag20]>;
569 Defs<[DSPOutFlag20]>;
573 Defs<[DSPOutFlag20]>;
577 Defs<[DSPOutFlag20]>;
581 IsCommutable, Defs<[DSPOutFlag20]>;
585 Defs<[DSPOutFlag20]>;
589 Defs<[DSPOutFlag20]>;
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DMipsDelaySlotFiller.cpp136 BitVector Defs, Uses; member in __anon2939609f0111::RegDefsUses
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon2939609f0111::MemDefsUses
346 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
355 Defs.set(Mips::RA); in init()
361 Defs.reset(Mips::AT); in init()
372 Defs.set(Mips::RA); in setCallerSaved()
373 Defs.set(Mips::RA_64); in setCallerSaved()
387 Defs |= CallerSavedRegs; in setCallerSaved()
400 Defs |= AllocSet.flip(); in setUnallocatableRegs()
429 Defs |= NewDefs; in update()
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DMicroMipsDSPInstrInfo.td189 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
191 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
193 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
227 Defs<[DSPOutFlag22]>;
230 Defs<[DSPOutFlag22]>;
233 Defs<[DSPOutFlag22]>;
236 Defs<[DSPOutFlag22]>;
261 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
264 Defs<[DSPOutFlag22]>;
266 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS()
106 InsertUsesDefs(LocalDefs, Defs); in INITIALIZE_PASS()
138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument
152 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions() local
209 Defs.clear(); in InsertITInstructions()
211 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
262 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCBoolRetToInt.cpp73 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
76 Defs.insert(V); in findAllDefs()
85 if (Defs.insert(Op).second) in findAllDefs()
88 return Defs; in findAllDefs()
220 auto Defs = findAllDefs(U); in runOnUse() local
223 if (llvm::none_of(Defs, isa<Instruction, Value *>)) in runOnUse()
229 for (Value *V : Defs) in runOnUse()
234 for (Value *V : Defs) in runOnUse()
245 for (Value *V : Defs) in runOnUse()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
483 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
487 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
488 while (!Defs.empty()) { in UpdatePhysRegDefs()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
490 Defs.pop_back(); in UpdatePhysRegDefs()
501 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
559 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
561 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
566 SmallVector<unsigned, 4> Defs; in runOnBlock() local
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DRegisterPressure.cpp485 for (const RegisterMaskPair &P : RegOpers.Defs) in collectInstr()
494 for (const RegisterMaskPair &P : RegOpers.Defs) in collectInstrLanes()
516 pushReg(Reg, RegOpers.Defs); in collectOperand()
548 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
582 for (auto RI = Defs.begin(); RI != Defs.end(); /*empty*/) { in detectDeadDefs()
591 RI = Defs.erase(RI); in detectDeadDefs()
603 for (auto I = Defs.begin(); I != Defs.end(); ) { in adjustLaneLiveness()
615 I = Defs.erase(I); in adjustLaneLiveness()
662 for (const RegisterMaskPair &P : RegOpers.Defs) in addInstruction()
772 for (const RegisterMaskPair &Def : RegOpers.Defs) { in recede()
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DMachineInstrBundle.cpp147 SmallVector<MachineOperand*, 4> Defs; in finalizeBundle() local
154 Defs.push_back(&MO); in finalizeBundle()
179 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in finalizeBundle()
180 MachineOperand &MO = *Defs[i]; in finalizeBundle()
207 Defs.clear(); in finalizeBundle()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
45 Defs[Hexagon::LC0].insert(Unconditional); in init()
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
49 Defs[Hexagon::LC1].insert(Unconditional); in init()
124 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
176 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
384 if (!Defs.count(P) || LatePreds.count(P)) { in checkPredicates()
397 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
496 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly() local
497 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DMemorySSAUpdater.cpp153 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
156 if (Defs) { in getPreviousDefInBlock()
161 if (Iter != Defs->rend()) in getPreviousDefInBlock()
180 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
182 if (Defs) { in getPreviousDefFromEnd()
183 CachedPreviousDef.insert({BB, &*Defs->rbegin()}); in getPreviousDefFromEnd()
184 return &*Defs->rbegin(); in getPreviousDefFromEnd()
261 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
262 (void)Defs; in insertUse()
263 assert((!Defs || (++Defs->begin() == Defs->end())) && in insertUse()
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DMemorySSA.cpp533 auto *Defs = MSSA.getBlockDefs(Node->getBlock()); in getWalkTarget() local
534 if (Defs) in getWalkTarget()
535 return &*Defs->rbegin(); in getWalkTarget()
1526 DefsList *Defs = nullptr; in buildMemorySSA() local
1537 if (!Defs) in buildMemorySSA()
1538 Defs = getOrCreateDefsList(&B); in buildMemorySSA()
1539 Defs->push_back(*MUD); in buildMemorySSA()
1604 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
1605 Defs->push_front(*NewAccess); in insertIntoListsForBlock()
1611 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td56 // AL is really implied by AX, but the registers in Defs must match the
59 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
67 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
72 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
78 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
84 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
94 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
102 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
110 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
70 let Defs = [AL], Uses = [DX] in
72 let Defs = [AX], Uses = [DX] in
75 let Defs = [EAX], Uses = [DX] in
79 let Defs = [AL] in
82 let Defs = [AX] in
85 let Defs = [EAX] in
409 let Defs = [EAX, EDX], Uses = [ECX] in
412 let Defs = [RAX, RDX], Uses = [ECX] in
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DX86InstrTSX.td27 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
35 let isPseudo = 1, Defs = [EAX] in {
42 let Defs = [EFLAGS] in
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ExecutionEngine/Orc/
DCompileOnDemandLayer.cpp244 IRMaterializationUnit::SymbolNameToDefinitionMap Defs) { in emitPartition() argument
254 assert(Defs.count(Name) && "No definition for symbol"); in emitPartition()
255 RequestedGVs.insert(Defs[Name]); in emitPartition()
267 Defs.clear(); in emitPartition()
275 std::move(TSM), R.getSymbols(), std::move(Defs), *this)); in emitPartition()

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