| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2771 ISD = ISD::FMINNUM; in getMinMaxReductionCost()
2778 {ISD::FMINNUM, MVT::v4f32, 4}, in getMinMaxReductionCost()
2782 {ISD::FMINNUM, MVT::v2f64, 3}, in getMinMaxReductionCost()
2794 {ISD::FMINNUM, MVT::v4f32, 2}, in getMinMaxReductionCost()
2811 {ISD::FMINNUM, MVT::v4f32, 1}, in getMinMaxReductionCost()
2812 {ISD::FMINNUM, MVT::v4f64, 1}, in getMinMaxReductionCost()
2813 {ISD::FMINNUM, MVT::v8f32, 2}, in getMinMaxReductionCost()
2844 {ISD::FMINNUM, MVT::v8f64, 1}, in getMinMaxReductionCost()
2845 {ISD::FMINNUM, MVT::v16f32, 2}, in getMinMaxReductionCost()
2853 {ISD::FMINNUM, MVT::v4f32, 4}, in getMinMaxReductionCost()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 72 FUNCTION(minnum, 2, 0, experimental_constrained_minnum, FMINNUM)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 652 FMINNUM, FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 1250 ISDs.push_back(ISD::FMINNUM);
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| D | TargetLowering.h | 2259 case ISD::FMINNUM: in isCommutativeBinOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 322 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
388 Opcode = ISD::FMINNUM; break; in mightUseCTR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 536 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
542 // The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
559 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
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| D | TargetSelectionDAG.td | 441 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 413 setOperationAction(ISD::FMINNUM, MVT::f32, Custom); in SITargetLowering()
415 setOperationAction(ISD::FMINNUM, MVT::f64, Custom); in SITargetLowering()
602 setOperationAction(ISD::FMINNUM, MVT::f16, Custom); in SITargetLowering()
609 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand); in SITargetLowering()
657 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom); in SITargetLowering()
659 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom); in SITargetLowering()
722 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
4084 case ISD::FMINNUM: in LowerOperation()
5808 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
8622 case ISD::FMINNUM: in fp16SrcZerosHighBits()
[all …]
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| D | AMDGPUISelLowering.cpp | 258 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
404 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering()
518 case ISD::FMINNUM: in fnegFoldsIntoOp()
3647 return ISD::FMINNUM; in inverseMinMax()
3648 case ISD::FMINNUM: in inverseMinMax()
3764 case ISD::FMINNUM: in performFNegCombine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 412 case ISD::FMINNUM: in LegalizeOp()
927 case ISD::FMINNUM: in Expand()
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| D | SelectionDAGDumper.cpp | 182 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 69 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
1131 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
2131 case ISD::FMINNUM: in PromoteFloatResult()
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| D | SelectionDAGBuilder.cpp | 3334 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
3336 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) in visitSelect()
3337 Opc = ISD::FMINNUM; in visitSelect()
3341 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? in visitSelect()
3342 ISD::FMINNUM : ISD::FMINIMUM; in visitSelect()
6220 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, in visitIntrinsicCall()
7648 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| D | LegalizeVectorTypes.cpp | 114 case ISD::FMINNUM: in ScalarizeVectorResult()
914 case ISD::FMINNUM: in SplitVectorResult()
2085 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM; in SplitVecOp_VECREDUCE()
2719 case ISD::FMINNUM: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3186 case ISD::FMINNUM: in ExpandNode()
3937 case ISD::FMINNUM: in ConvertNodeToLibcall()
4451 case ISD::FMINNUM: in PromoteNode()
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| D | TargetLowering.cpp | 6314 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ? in expandFMINNUM_FMAXNUM()
6341 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM; in expandFMINNUM_FMAXNUM()
6356 Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in expandFMINNUM_FMAXNUM()
7626 BaseOpcode = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM; in expandVecReduce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 168 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in RISCVTargetLowering()
185 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in RISCVTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 546 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SystemZTargetLowering()
551 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
556 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in SystemZTargetLowering()
561 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
566 setOperationAction(ISD::FMINNUM, MVT::f128, Legal); in SystemZTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 639 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1588 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in HexagonTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 341 setOperationAction(ISD::FMINNUM, VT, Legal); in addMVEVectorTypes()
723 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); in ARMTargetLowering()
1382 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in ARMTargetLowering()
1385 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1387 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1398 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in ARMTargetLowering()
1434 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1436 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal); in ARMTargetLowering()
3748 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 573 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) { in NVPTXTargetLowering()
579 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in NVPTXTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 452 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
513 setOperationAction(ISD::FMINNUM, Ty, Legal); in AArch64TargetLowering()
530 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); in AArch64TargetLowering()
935 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
11025 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 2121 // FastEmit functions for ISD::FMINNUM.
3287 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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