| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 666 FSINCOS, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 200 case ISD::FSINCOS: return "fsincos"; in getOperationName()
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| D | LegalizeDAG.cpp | 2269 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3197 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3201 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
3972 case ISD::FSINCOS: in ConvertNodeToLibcall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 891 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| D | X86InstrFPStack.td | 748 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
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| D | X86ISelLowering.cpp | 538 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in X86TargetLowering()
575 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in X86TargetLowering()
590 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
656 setOperationAction(ISD::FSINCOS, MVT::f80, Expand); in X86TargetLowering()
707 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall); in X86TargetLowering()
758 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
1951 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in X86TargetLowering()
1952 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in X86TargetLowering()
28652 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG); in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 270 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
414 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
415 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
416 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
558 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
559 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
561 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
562 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
721 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
3258 case ISD::FSINCOS: in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1618 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1623 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
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| /third_party/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 766 #define FSINCOS CHOICE(fsincos, fsincos, fsincos) macro
1479 #define FSINCOS fsincos macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 438 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in MipsTargetLowering()
439 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in MipsTargetLowering()
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| D | MipsSEISelLowering.cpp | 150 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in MipsSETargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1327 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in ARMTargetLowering()
1328 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in ARMTargetLowering()
1370 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in ARMTargetLowering()
1371 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in ARMTargetLowering()
1409 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in ARMTargetLowering()
9368 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 164 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, in RISCVTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 275 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
280 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 459 setOperationAction(ISD::FSINCOS, VT, Expand); in SystemZTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 8803 case ISD::FSINCOS: in isCanonicalized()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmWriter.inc | 2677 16356U, // FSINCOS
17928 0U, // FSINCOS
33179 0U, // FSINCOS
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| D | X86GenAsmWriter1.inc | 2386 13000U, // FSINCOS
17637 0U, // FSINCOS
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| D | X86GenAsmMatcher.inc | 8756 { 2814 /* fsincos */, X86::FSINCOS, Convert_NoOperands, AMFBS_None, { }, },
23328 { 2814 /* fsincos */, X86::FSINCOS, Convert_NoOperands, AMFBS_None, { }, },
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| D | X86GenDisassemblerTables.inc | 11407 /* FSINCOS */
77300 0x3f2, /* FSINCOS */
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| D | X86GenInstrInfo.inc | 1025 FSINCOS = 1010,
18710 …, 0x364000007bULL, ImplicitList17, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #1010 = FSINCOS
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