/third_party/mesa3d/src/mesa/main/ |
D | extensions_table.h | 4 #define GLC 0 macro 9 EXT(3DFX_texture_compression_FXT1 , TDFX_texture_compression_FXT1 , GLL, GLC, x… 12 EXT(AMD_conservative_depth , ARB_conservative_depth , GLL, GLC, x… 13 EXT(AMD_depth_clamp_separate , AMD_depth_clamp_separate , GLL, GLC, x… 14 EXT(AMD_draw_buffers_blend , ARB_draw_buffers_blend , GLL, GLC, x… 15 EXT(AMD_framebuffer_multisample_advanced , AMD_framebuffer_multisample_advanced , GLL, GLC, x… 16 EXT(AMD_gpu_shader_int64 , ARB_gpu_shader_int64 , x , GLC, x… 17 EXT(AMD_multi_draw_indirect , ARB_draw_indirect , GLL, GLC, x… 18 EXT(AMD_performance_monitor , AMD_performance_monitor , GLL, GLC, x… 19 EXT(AMD_pinned_memory , AMD_pinned_memory , GLL, GLC, x… [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | MIMGInstructions.td | 228 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 240 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 253 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 321 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 334 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 347 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 410 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 439 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe); 454 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 512 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, [all …]
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D | SMInstructions.td | 438 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc, DLC:$dlc); 444 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc); 491 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc); 494 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc); 512 … = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc); 516 …let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$gl… 665 let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc, DLC:$dlc); 856 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc); 859 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc); 876 … = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc); [all …]
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D | AMDGPUISelDAGToDAG.cpp | 210 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC, 213 SDValue &SOffset, SDValue &Offset, SDValue &GLC, 227 SDValue &Offset, SDValue &GLC, SDValue &SLC, 1342 SDValue &GLC, SDValue &SLC, in SelectMUBUF() argument 1351 if (!GLC.getNode()) in SelectMUBUF() 1352 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1); in SelectMUBUF() 1435 SDValue &Offset, SDValue &GLC, in SelectMUBUFAddr64() argument 1445 GLC, SLC, TFE, DLC, SWZ)) in SelectMUBUFAddr64() 1467 SDValue GLC, TFE, DLC, SWZ; in SelectMUBUFAddr64() local 1469 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE, DLC, SWZ); in SelectMUBUFAddr64() [all …]
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D | SILoadStoreOptimizer.cpp | 125 bool GLC; member 511 GLC = TII.getNamedOperand(*I, AMDGPU::OpName::glc)->getImm(); in setMI() 768 CI.GLC == Paired.GLC && CI.DLC == Paired.DLC && in offsetsCanBeCombined() 1194 .addImm(CI.GLC) // glc in mergeSBufferLoadImmPair() 1253 .addImm(CI.GLC) // glc in mergeBufferLoadPair() 1319 .addImm(CI.GLC) // glc in mergeTBufferLoadPair() 1398 .addImm(CI.GLC) // glc in mergeTBufferStorePair() 1557 .addImm(CI.GLC) // glc in mergeBufferStorePair()
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D | FLATInstructions.td | 145 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)), 166 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)), 200 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc), 201 (ins VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)), 216 …(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc… 217 (ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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D | BUFInstructions.td | 144 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz), 146 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz) 150 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc, 153 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc, 403 offset:$offset, GLC:$glc, SLC:$slc), 405 offset:$offset, GLC:$glc, SLC:$slc) 409 SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc), 411 SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc) 603 … (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc, SWZ:$swz),
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D | SIISelLowering.h | 63 SDValue GLC, SDValue DLC, SelectionDAG &DAG) const;
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D | SIISelLowering.cpp | 5212 SDValue *GLC, SDValue *SLC, SDValue *DLC) { in parseCachePolicy() argument 5217 if (GLC) { in parseCachePolicy() 5218 *GLC = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32); in parseCachePolicy() 5572 SDValue GLC; in lowerImage() local 5576 GLC = True; // TODO no-return optimization in lowerImage() 5581 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, &GLC, &SLC, in lowerImage() 5604 Ops.push_back(GLC); in lowerImage() 5658 SDValue Offset, SDValue GLC, SDValue DLC, in lowerSBuffer() argument 5676 GLC, in lowerSBuffer() 5712 unsigned CachePolicy = cast<ConstantSDNode>(GLC)->getZExtValue(); in lowerSBuffer() [all …]
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D | SIInstrInfo.td | 1063 def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
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D | SIInstrInfo.cpp | 4775 if (const MachineOperand *GLC = in legalizeOperands() local 4777 MIB.addImm(GLC->getImm()); in legalizeOperands()
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/third_party/mesa3d/src/amd/compiler/ |
D | README-ISA.md | 126 ## RDNA L0, L1 cache and DLC, GLC bits 130 GLC bits that interact with the cache. 133 * GLC ("globally coherent") bit: controls the L0 cache
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/third_party/mesa3d/docs/relnotes/ |
D | 19.0.0.rst | 2004 - amd/common/vi+: enable SMEM loads with GLC=1
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D | 22.2.0.rst | 3911 - ac/llvm: don't set GLC for stores on gfx11 5417 - aco: do not set GLC stores on GFX11
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/third_party/openh264/res/ |
D | Cisco_Absolute_Power_1280x720_30fps.yuv | 3873 …!! !#!!/GLC;79:BINOPQRR[]__^`_^…
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