| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3086 const LLT HalfTy, const LLT AmtTy) { in narrowScalarShiftByConstant() argument
3088 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
3089 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
3098 LLT NVT = HalfTy; in narrowScalarShiftByConstant()
3099 unsigned NVTBits = HalfTy.getSizeInBits(); in narrowScalarShiftByConstant()
3198 const LLT HalfTy = LLT::scalar(NewBitSize); in narrowScalarShift() local
3204 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); in narrowScalarShift()
3212 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
3213 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
3227 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 678 LLT HalfTy, in split64BitValueForMapping() argument
680 assert(HalfTy.getSizeInBits() == 32); in split64BitValueForMapping()
682 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
683 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
1587 LLT HalfTy = getHalfSizedType(DstTy); in applyMappingImpl() local
1600 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); in applyMappingImpl()
1602 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingImpl()
1606 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg()); in applyMappingImpl()
1608 setRegsToType(MRI, Src2Regs, HalfTy); in applyMappingImpl()
1610 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl()
[all …]
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| D | AMDGPURegisterBankInfo.h | 120 LLT HalfTy,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 231 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2); in typeSplit() local
232 return { HalfTy, HalfTy }; in typeSplit()
1111 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxConcatVectors() local
1112 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1114 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1474 MVT HalfTy = typeSplit(ResTy).first; in SplitHvxPairOp() local
1475 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL); in SplitHvxPairOp()
1476 SDValue H = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsH); in SplitHvxPairOp()
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| D | HexagonISelDAGToDAGHVX.cpp | 1012 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), in materialize() local
1016 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1168 MVT HalfTy = getSingleVT(MVT::i8); in packp() local
1171 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) }; in packp()
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| D | HexagonISelLowering.cpp | 2315 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2); in buildVector64() local
2318 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG); in buildVector64()
2321 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG); in buildVector64()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | LLVMContextImpl.cpp | 27 HalfTy(C, Type::HalfTyID), in LLVMContextImpl()
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| D | Type.cpp | 167 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
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| D | LLVMContextImpl.h | 1320 Type VoidTy, LabelTy, HalfTy, FloatTy, DoubleTy, MetadataTy, TokenTy;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 214 LLT HalfTy, LLT ShiftAmtTy);
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