Searched refs:HwMode (Results 1 – 14 of 14) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVRegisterInfo.cpp | 38 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() argument 40 /*PC*/0, HwMode) {} in RISCVRegisterInfo()
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D | RISCV.td | 67 def RV64 : HwMode<"+64bit">; 68 def RV32 : HwMode<"-64bit">;
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D | RISCVRegisterInfo.h | 25 RISCVRegisterInfo(unsigned HwMode);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.h | 31 HexagonRegisterInfo(unsigned HwMode);
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D | HexagonRegisterInfo.cpp | 44 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() argument 46 0/*PC*/, HwMode) {} in HexagonRegisterInfo()
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D | Hexagon.td | 95 def Hvx64: HwMode<"+hvx-length64b">; 96 def Hvx128: HwMode<"+hvx-length128b">;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | TargetRegisterInfo.h | 245 unsigned HwMode; variable 654 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
D | Target.td | 23 class HwMode<string FS> { 36 def DefaultMode : HwMode<"">; 43 class HwModeSelect<list<HwMode> Ms> { 44 list<HwMode> Modes = Ms; 52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts> 67 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []> 446 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies 448 // to encode and decode based on HwMode. 449 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []> 466 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | TargetRegisterInfo.cpp | 53 RCInfos(RCIs), HwMode(Mode) { in TargetRegisterInfo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
D | PPCGenRegisterInfo.inc | 3843 unsigned PC = 0, unsigned HwMode = 0); 5679 unsigned PC, unsigned HwMode) 5682 LaneBitmask(0xFFFFFFC0), RegClassInfos, HwMode) {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenRegisterInfo.inc | 3809 unsigned PC = 0, unsigned HwMode = 0); 7353 unsigned PC, unsigned HwMode) 7356 LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
D | X86GenRegisterInfo.inc | 4315 unsigned PC = 0, unsigned HwMode = 0); 9932 unsigned PC, unsigned HwMode) 9935 LaneBitmask(0xFFFFFFB0), RegClassInfos, HwMode) {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenRegisterInfo.inc | 3581 unsigned PC = 0, unsigned HwMode = 0); 15956 unsigned PC, unsigned HwMode) 15959 LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenRegisterInfo.inc | 5029 unsigned PC = 0, unsigned HwMode = 0); 20361 unsigned PC, unsigned HwMode) 20364 LaneBitmask(0xFFFFFFB6), RegClassInfos, HwMode) {
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