| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 407 INSERT_SUBVECTOR, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 781 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1350 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1432 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1620 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1753 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1754 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom); in X86TargetLowering()
1784 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal); in X86TargetLowering()
1785 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal); in X86TargetLowering()
1988 setTargetDAGCombine(ISD::INSERT_SUBVECTOR); in X86TargetLowering()
5685 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()
[all …]
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| D | X86ISelDAGToDAG.cpp | 718 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 97 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
188 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1565 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
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| D | HexagonISelLowering.cpp | 1492 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1541 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
2904 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 1091 ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), Src, in ExpandANY_EXTEND_VECTOR_INREG()
1151 ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), Src, in ExpandZERO_EXTEND_VECTOR_INREG()
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| D | SelectionDAGDumper.cpp | 283 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
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| D | DAGCombiner.cpp | 1605 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
17488 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
18283 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
18628 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
19610 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
19619 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
19622 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), in visitINSERT_SUBVECTOR()
19628 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
19630 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, in visitINSERT_SUBVECTOR()
19667 if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) { in visitINSERT_SUBVECTOR()
[all …]
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| D | LegalizeVectorTypes.cpp | 834 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1147 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
3196 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
3199 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4292 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp, in WidenVecOp_EXTEND()
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| D | SelectionDAG.cpp | 2627 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
3951 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5446 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
5614 case ISD::INSERT_SUBVECTOR: { in getNode()
9475 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
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| D | TargetLowering.cpp | 921 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
2325 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
2347 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
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| D | LegalizeDAG.cpp | 3019 case ISD::INSERT_SUBVECTOR: in ExpandNode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 272 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
338 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom); in SITargetLowering()
339 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom); in SITargetLowering()
340 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom); in SITargetLowering()
341 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom); in SITargetLowering()
344 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom); in SITargetLowering()
345 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom); in SITargetLowering()
346 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom); in SITargetLowering()
347 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom); in SITargetLowering()
534 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
[all …]
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| D | AMDGPUISelLowering.cpp | 1442 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1444 Join = DAG.getNode(HiVT.isVector() ? ISD::INSERT_SUBVECTOR in SplitVectorLoad()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 656 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 545 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
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| D | AArch64ISelLowering.cpp | 6513 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenDAGISel.inc | 59435 /*130476*/ /*SwitchOpcode*/ 16|128,1/*144*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->130624
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