| /third_party/mesa3d/src/intel/compiler/ |
| D | test_eu_validate.cpp | 1255 #define INST(dst_type, src_type, dst_stride, expected_result) \ in TEST_P() macro
1263 INST(B, Q, 1, false), in TEST_P()
1264 INST(B, UQ, 1, false), in TEST_P()
1265 INST(B, DF, 1, false), in TEST_P()
1266 INST(UB, Q, 1, false), in TEST_P()
1267 INST(UB, UQ, 1, false), in TEST_P()
1268 INST(UB, DF, 1, false), in TEST_P()
1270 INST(B, Q, 2, false), in TEST_P()
1271 INST(B, UQ, 2, false), in TEST_P()
1272 INST(B , DF, 2, false), in TEST_P()
[all …]
|
| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_exec.h | 51 #define TGSI_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\ argument
52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
54 #define TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\ argument
55 if (TGSI_IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
57 #define TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( INST, CHAN )\ argument
59 TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )
61 #define TGSI_IS_DST1_CHANNEL_ENABLED( INST, CHAN )\ argument
62 ((INST)->Dst[1].Register.WriteMask & (1 << (CHAN)))
64 #define TGSI_IF_IS_DST1_CHANNEL_ENABLED( INST, CHAN )\ argument
65 if (TGSI_IS_DST1_CHANNEL_ENABLED( INST, CHAN ))
[all …]
|
| /third_party/icu/tools/multi/proj/provider/ |
| D | Makefile | 75 INST=$(M_TMP)/$(P_PREFIX)ins macro
96 ALLDIRS=$(INST) $(BUILD) $(SRC) $(GLOUT) $(OUT) $(GLOUT)/$(PLUGLIB) $(OUT)/$(PLUGLIB)/bin
98 INST_ICU=$(PLUGLIB_AVAILABLE:%=$(INST)/%/$(OK))
293 $(INST)/%/ok: $(BUILD)/%/ok
296 mkdir -p $(INST)/$*
314 …*/$(SOURCE) $*) $(CONFIGURE_OPTS) --srcdir=$(TOP)/$(SRC)/$*/$(SOURCE) --prefix=$(TOP)/$(INST)/$* ))
|
| /third_party/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_fmt_def.inc | 270 BC_FIELD(ALU_WORD1_OP2, ALU_INST, INST, 17, 8)
285 BC_FIELD(ALU_WORD1_OP2, ALU_INST, INST, 17, 7)
300 BC_FIELD(ALU_WORD1_OP2_MOVA, ALU_INST, INST, 17, 7)
315 BC_FIELD(ALU_WORD1_OP2_EXEC_MASK, ALU_INST, INST, 17, 7)
328 BC_FIELD(ALU_WORD1_OP3, ALU_INST, INST, 17, 13)
356 BC_FIELD(ALU_WORD1_LDS_IDX_OP, ALU_INST, INST, 17, 13)
387 BC_FIELD(VTX_WORD0, VC_INST, INST, 4, 0)
398 BC_FIELD(VTX_WORD0, VC_INST, INST, 4, 0)
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1065 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
1079 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
3315 multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
3316 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
3317 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
3318 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
3319 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
3320 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
3321 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
3324 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
[all …]
|
| D | AArch64InstrFormats.td | 3240 class ROInstAlias<string asm, RegisterOperand regtype, Instruction INST>
3242 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
7815 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
7820 (!cast<Instruction>(INST # v2i32_indexed)
7824 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
7832 (!cast<Instruction>(INST # "v4i32_indexed")
7836 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
7843 (!cast<Instruction>(INST # "v2i64_indexed")
7847 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
7853 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
[all …]
|
| /third_party/python/Lib/ |
| D | pickle.py | 139 INST = b'i' # build & push class instance variable
1502 dispatch[INST[0]] = load_inst
|
| /third_party/libsnd/ |
| D | NEWS | 183 * Fix bug in INST and MARK chunk writing for AIFF files.
|
| /third_party/python/Modules/ |
| D | _pickle.c | 66 INST = 'i', enumerator
6911 OP(INST, load_inst) in load()
|