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Searched refs:INVALID_REG (Results 1 – 16 of 16) sorted by relevance

/third_party/mesa3d/src/freedreno/ir3/
Dir3_assembler.c51 info->numwg = INVALID_REG; in ir3_parse_asm()
54 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
Dir3_lower_spill.c59 ir3_src_create(mov, INVALID_REG, IR3_REG_IMMED)->uim_val = val; in set_base_reg()
78 ir3_src_create(mov, INVALID_REG, IR3_REG_IMMED)->uim_val = 0; in reset_base_reg()
Dir3_spill.c360 ir3_src_create(remat, INVALID_REG, reg->instr->srcs[i]->flags); in rematerialize()
573 if (dst->instr->opc == OPC_META_INPUT && dst->num != INVALID_REG) { in insert_dst()
714 struct ir3_register *mov_src = ir3_src_create(mov, INVALID_REG, src->flags); in materialize_pcopy_src()
746 ir3_src_create(spill, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in spill()
750 struct ir3_register *src = ir3_src_create(spill, INVALID_REG, src_flags); in spill()
751 ir3_src_create(spill, INVALID_REG, IR3_REG_IMMED)->uim_val = elems; in spill()
860 struct ir3_register *src = ir3_src_create(split, INVALID_REG, def->flags); in split()
890 ir3_src_create(collect, INVALID_REG, parent_def->flags)->def = srcs[i]; in extract()
920 ir3_src_create(reload, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in reload()
922 ir3_src_create(reload, INVALID_REG, IR3_REG_IMMED); in reload()
[all …]
Dir3_ra.c1600 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1611 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1797 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1815 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1831 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1895 assert(src->num != INVALID_REG); in handle_chmask()
2061 struct ir3_register *dst_reg = ir3_dst_create(pcopy, INVALID_REG, flags); in insert_liveout_copy()
2070 struct ir3_register *src_reg = ir3_src_create(pcopy, INVALID_REG, flags); in insert_liveout_copy()
2413 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
Dir3_context.c595 src->array.base = INVALID_REG; in ir3_create_array_load()
630 dst->array.base = INVALID_REG; in ir3_create_array_store()
660 dst->array.base = INVALID_REG; in ir3_create_array_store()
Dinstr-a3xx.h494 #define INVALID_REG regid(63, 0) macro
495 #define VALIDREG(r) ((r) != INVALID_REG)
Dir3_print.c268 if (reg->num != INVALID_REG && !(reg->flags & IR3_REG_ARRAY)) in print_ssa_name()
319 if (reg->array.base != INVALID_REG) in print_reg_name()
Dir3_array_to_ssa.c126 src_reg = ir3_src_create(phi, INVALID_REG, flags | IR3_REG_SSA); in read_value_beginning()
Dir3_lower_subgroups.c67 mov, INVALID_REG, (dst->flags & IR3_REG_HALF) | IR3_REG_IMMED); in mov_immed()
Dir3.h1914 reg = ir3_src_create(instr, INVALID_REG, IR3_REG_SSA | flags); in __ssa_src()
1923 struct ir3_register *reg = ir3_dst_create(instr, INVALID_REG, IR3_REG_SSA); in __ssa_dst()
Dir3_compiler_nir.c1904 ir3_src_create(mov, INVALID_REG, IR3_REG_SSA | src_flags); in create_multidst_mov()
3420 ir3_src_create(continue_phi, INVALID_REG, phi->dsts[0]->flags); in read_phi_src()
3460 ir3_src_create(phi, INVALID_REG, phi->dsts[0]->flags); in resolve_phis()
4919 so->inputs[i].regid = INVALID_REG; in ir3_compile_shader_nir()
4921 so->outputs[i].regid = INVALID_REG; in ir3_compile_shader_nir()
Dir3_shader.c211 info.numwg = INVALID_REG; in try_override_shader_variant()
/third_party/mesa3d/src/freedreno/computerator/
Da6xx.c269 if (ir3_kernel->info.numwg != INVALID_REG) { in cs_const_emit()
278 if (kernel->buf_addr_regs[i] != INVALID_REG) { in cs_const_emit()
Da4xx.c169 if (kernel->buf_addr_regs[i] != INVALID_REG) { in emit_const()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_program.c990 assert(flags_regid != INVALID_REG); in setup_stateobj()
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c821 if (k >= v->outputs_count || v->outputs[k].regid == INVALID_REG) in tu6_setup_streamout()
1173 assert(flags_regid != INVALID_REG); in tu6_emit_vpc()