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Searched refs:InstrStage (Results 1 – 25 of 41) sorted by relevance

12

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCSchedule440.td107 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
108 InstrStage<1, [P440_IRACC, P440_LRACC]>,
109 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
110 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
111 InstrStage<1, [P440_IWB, P440_JWB]>],
115 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
116 InstrStage<1, [P440_IRACC, P440_LRACC]>,
117 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
118 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
119 InstrStage<1, [P440_IWB, P440_JWB]>],
[all …]
DPPCScheduleP7.td82 InstrItinData<IIC_IntSimple , [InstrStage<1, [P7_DU1, P7_DU2,
84 InstrStage<1, [P7_FX1, P7_FX2,
87 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
89 InstrStage<1, [P7_FX1, P7_FX2]>],
91 InstrItinData<IIC_IntISEL, [InstrStage<1, [P7_DU1], 0>,
92 InstrStage<1, [P7_FX1, P7_FX2], 0>,
93 InstrStage<1, [P7_BRU]>],
95 InstrItinData<IIC_IntCompare , [InstrStage<1, [P7_DU1, P7_DU2,
97 InstrStage<1, [P7_FX1, P7_FX2]>],
100 InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>,
[all …]
DPPCScheduleP8.td57 InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
59 InstrStage<1, [P8_FXU1, P8_FXU2,
63 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
65 InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
68 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
69 InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
70 InstrStage<1, [P8_BRU]>],
72 InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
74 InstrStage<1, [P8_FXU1, P8_FXU2]>],
76 InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
[all …]
DPPCScheduleE5500.td50 InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
51 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
55 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
56 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
60 InstrItinData<IIC_IntISEL, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
61 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
66 InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
67 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
71 InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
72 InstrStage<1, [E5500_CFX_0], 0>,
[all …]
DPPCScheduleE500mc.td46 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
47 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
51 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
52 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
56 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
57 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
62 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
63 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
67 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
68 InstrStage<1, [E500mc_CFX_0], 0>,
[all …]
DPPCScheduleG4.td27 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
28 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
29 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
30 InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>,
31 InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>,
32 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>,
33 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>,
34 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>,
35 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>,
36 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>,
[all …]
DPPCScheduleE500.td41 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
42 InstrStage<1, [E500_SU0, E500_SU1]>],
46 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
47 InstrStage<1, [E500_SU0, E500_SU1]>],
51 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
52 InstrStage<1, [E500_SU0, E500_SU1]>],
57 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
58 InstrStage<1, [E500_SU0, E500_SU1]>],
62 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
63 InstrStage<1, [E500_MU], 0>,
[all …]
DPPCScheduleG5.td28 InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
29 InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
30 InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>,
31 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
32 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
33 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
34 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
35 InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
36 InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>,
37 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
[all …]
DPPCScheduleG4Plus.td29 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4P_IU1, G4P_IU2,
31 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4P_IU1, G4P_IU2,
33 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4P_IU1, G4P_IU2,
35 InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>,
36 InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>,
37 InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>,
38 InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>,
39 InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>,
40 InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>,
41 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>,
[all …]
DPPCScheduleG3.td22 InstrItinData<IIC_IntSimple , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
23 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
24 InstrItinData<IIC_IntCompare , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
25 InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>,
26 InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>,
27 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>,
28 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>,
29 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>,
30 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>,
31 InstrItinData<IIC_IntRotate , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
[all …]
DPPCScheduleA2.td27 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
29 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
31 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
33 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
35 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
37 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
39 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
41 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
43 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
45 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleA8.td30 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
33 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
34 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
35 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
36 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
37 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
40 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
41 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
42 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
43 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
[all …]
DARMScheduleA9.td45 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
46 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
47 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
48 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
49 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
50 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
51 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
52 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
53 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
54 InstrStage<1, [A9_ALU0, A9_ALU1]>,
[all …]
DARMScheduleV6.td24 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
27 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
28 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
29 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
30 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
33 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
34 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
35 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
36 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
39 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepIICHVX.td106 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
107 InstrStage<1, [CVI_XLSHF]>], [9, 5],
111 [InstrStage<1, [SLOT1], 0>,
112 InstrStage<1, [CVI_LD], 0>,
113 InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
117 [InstrStage<1, [SLOT1], 0>,
118 InstrStage<1, [CVI_LD], 0>,
119 InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
123 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
124 InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
[all …]
DHexagonDepIICScalar.td185 InstrItinData <tc_002cb246, [InstrStage<1, [SLOT2, SLOT3]>]>,
186 InstrItinData <tc_0371abea, [InstrStage<1, [SLOT0, SLOT1]>]>,
187 InstrItinData <tc_05c070ec, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
188 InstrItinData <tc_05d3a09b, [InstrStage<1, [SLOT2, SLOT3]>]>,
189 InstrItinData <tc_0663f615, [InstrStage<1, [SLOT2, SLOT3]>]>,
190 InstrItinData <tc_096199d3, [InstrStage<1, [SLOT0]>]>,
191 InstrItinData <tc_0a705168, [InstrStage<1, [SLOT0, SLOT1]>]>,
192 InstrItinData <tc_0ae0825c, [InstrStage<1, [SLOT2, SLOT3]>]>,
193 InstrItinData <tc_0b2be201, [InstrStage<1, [SLOT0, SLOT1]>]>,
194 InstrItinData <tc_0d8f5752, [InstrStage<1, [SLOT3]>]>,
[all …]
DHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
19 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
20 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
26 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
28 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
DHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>]>,
17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>,
18 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>
24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
DHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
16 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
17 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
DHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
16 InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
25 [InstrStage<1, [SLOT0], 0>,
26 InstrStage<1, [SLOT1], 0>,
27 InstrStage<1, [CVI_ST], 0>,
28 InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSchedule.td384 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
385 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
386 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
387 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
388 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
389 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcSchedule.td44 InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
45 InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
46 InstrItinData<IIC_fpu_normal_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
47 InstrItinData<IIC_fpu_fast_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
48 InstrItinData<IIC_jmp_or_call, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
49 InstrItinData<IIC_ldd, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
50 InstrItinData<IIC_st, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
51 InstrItinData<IIC_std, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
52 InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [5, 1]>,
53 InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [5, 1]>,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenSubtargetInfo.inc366 extern const llvm::InstrStage PPCStages[] = {
367 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
368 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_LRACC, -1, (llvm::InstrStage::R…
369 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_IRACC | PPC440ItinerariesFU::P4…
370 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_IRACC, -1, (llvm::InstrStage::R…
371 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_LRACC, -1, (llvm::InstrStage::R…
372 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_LRACC, -1, (llvm::InstrStage::R…
373 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_IRACC, -1, (llvm::InstrStage::R…
374 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_FRACC, -1, (llvm::InstrStage::R…
375 …InstrStage::ReservationKinds)0 }, { 1, PPC440ItinerariesFU::P440_FRACC, -1, (llvm::InstrStage::R…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600Schedule.td31 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
32 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
33 InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
34 InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>,
35 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
43 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
44 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
45 InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
46 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp45 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
46 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
128 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
147 case InstrStage::Required: in getHazardType()
151 case InstrStage::Reserved: in getHazardType()
187 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction()
198 case InstrStage::Required: in EmitInstruction()
202 case InstrStage::Reserved: in EmitInstruction()
215 if (IS->getReservationKind() == InstrStage::Required) in EmitInstruction()

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