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Searched refs:IssueWidth (Results 1 – 25 of 70) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp74 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
105 if (IssueWidth == 0) in atIssueLimit()
108 return IssueCount == IssueWidth; in atIssueLimit()
DTargetSchedule.cpp71 ResourceLCM = SchedModel.IssueWidth; in init()
77 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCSchedule.cpp106 return ((double)SCDesc.NumMicroOps) / SM.IssueWidth; in getReciprocalThroughput()
119 return 1.0 / IssueWidth; in getReciprocalThroughput()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86PadShortFunction.cpp225 unsigned IssueWidth = TSM.getIssueWidth(); in addPadding() local
227 for (unsigned i = 0, e = IssueWidth * NOOPsToAdd; i != e; ++i) in addPadding()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DScoreboardHazardRecognizer.h99 unsigned IssueWidth = 0; variable
DTargetSchedule.h99 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonScheduleV62.td28 let IssueWidth = 4;
DHexagonScheduleV5.td37 let IssueWidth = 4;
DHexagonScheduleV65.td31 let IssueWidth = 4;
DHexagonScheduleV66.td31 let IssueWidth = 4;
DHexagonScheduleV55.td39 let IssueWidth = 4;
DHexagonScheduleV60.td72 let IssueWidth = 4;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiSchedule.td39 let IssueWidth = 1;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCSchedule.h256 unsigned IssueWidth; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/
DDispatchStage.cpp35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td159 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
DPPCScheduleG5.td118 let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
DPPCScheduleE500.td271 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td19 let IssueWidth = 8; // 8 uops are dispatched per cycle.
DAArch64SchedKryo.td20 let IssueWidth = 5; // 5-wide issue for expanded uops
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleM4.td14 let IssueWidth = 1; // Only IT can be dual-issued, so assume single-issue
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSchedRocket32.td16 let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
DRISCVSchedRocket64.td16 let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSISchedule.td64 let IssueWidth = 1;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetItinerary.td89 // global IssueWidth property, which constrains the number of microops

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