Searched refs:MTBUF (Results 1 – 15 of 15) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 61 MTBUF = 9 variable in Format
96 elif self == Format.MTBUF:
1376 MTBUF = { variable
1394 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MTBUF:
1395 opcode(name, gfx7, gfx9, gfx10, Format.MTBUF, InstrClass.VMem)
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| D | aco_opt_value_numbering.cpp | 108 case Format::MTBUF: return hash_murmur_32<MTBUF_instruction>(instr); in operator ()()
252 case Format::MTBUF: { in operator ()()
350 case Format::MTBUF: in can_eliminate()
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| D | aco_ir.h | 81 MTBUF = 9, enumerator
1137 constexpr bool isMTBUF() const noexcept { return format == Format::MTBUF; } in isMTBUF()
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| D | aco_insert_waitcnt.cpp | 685 case Format::MTBUF: in gen()
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| D | aco_ir.cpp | 193 case Format::MTBUF: return instr->mtbuf().sync; in get_sync_info()
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| D | aco_print_ir.cpp | 503 case Format::MTBUF: { in print_instr_format_specific()
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| D | aco_assembler.cpp | 411 case Format::MTBUF: { in emit_instruction()
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| D | aco_validate.cpp | 564 case Format::MTBUF: in validate_ir()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 39 field bit MTBUF = 0;
151 let TSFlags{17} = MTBUF;
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| D | SIDefines.h | 46 MTBUF = 1 << 17, enumerator
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| D | SIInstrInfo.h | 454 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
458 return get(Opcode).TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
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| D | BUFInstructions.td | 54 // MTBUF classes
86 let MTBUF = 1;
1101 // MTBUF Instructions
1683 // MTBUF Patterns
2091 // MTBUF - GFX10.
2124 // MTBUF - GFX6, GFX7, GFX10.
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| /third_party/mesa3d/docs/relnotes/ |
| D | 19.3.0.rst | 3288 - aco: Support GFX10 MTBUF in aco_assembler.
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| D | 20.2.0.rst | 4312 - aco: fix off-by-one error with 16-bit MTBUF opcodes on GFX10
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| D | 21.1.0.rst | 4789 - aco: fix NSA MIMG followed by MUBUF/MTBUF
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