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Searched refs:MVT (Results 1 – 25 of 247) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); in getArithmeticInstrCost()
186 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
187 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
188 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw in getArithmeticInstrCost()
200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. in getArithmeticInstrCost()
201 { ISD::FMUL, MVT::f64, 2 }, // mulsd in getArithmeticInstrCost()
202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd in getArithmeticInstrCost()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h30 class MVT {
267 constexpr MVT() = default;
268 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() function
270 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
271 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
272 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
273 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
274 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
275 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
279 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp161 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
162 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
163 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
168 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); in getCastInstrCost()
182 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
183 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
184 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
185 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
186 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
187 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp126 case MVT::ppcf128: return "ppcf128"; in getEVTString()
127 case MVT::isVoid: return "isVoid"; in getEVTString()
128 case MVT::Other: return "ch"; in getEVTString()
129 case MVT::Glue: return "glue"; in getEVTString()
130 case MVT::x86mmx: return "x86mmx"; in getEVTString()
131 case MVT::Metadata:return "Metadata"; in getEVTString()
132 case MVT::Untyped: return "Untyped"; in getEVTString()
133 case MVT::exnref : return "exnref"; in getEVTString()
145 case MVT::isVoid: return Type::getVoidTy(Context); in getTypeForEVT()
146 case MVT::i1: return Type::getInt1Ty(Context); in getTypeForEVT()
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DTargetLoweringBase.cpp221 if (OpVT == MVT::f16) { in getFPEXT()
222 if (RetVT == MVT::f32) in getFPEXT()
224 } else if (OpVT == MVT::f32) { in getFPEXT()
225 if (RetVT == MVT::f64) in getFPEXT()
227 if (RetVT == MVT::f128) in getFPEXT()
229 if (RetVT == MVT::ppcf128) in getFPEXT()
231 } else if (OpVT == MVT::f64) { in getFPEXT()
232 if (RetVT == MVT::f128) in getFPEXT()
234 else if (RetVT == MVT::ppcf128) in getFPEXT()
236 } else if (OpVT == MVT::f80) { in getFPEXT()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp302 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
303 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
304 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
305 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
308 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
309 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
310 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
311 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
312 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
313 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
[all …]
DAArch64ISelDAGToDAG.cpp162 template<MVT::SimpleValueType VT>
167 template<MVT::SimpleValueType VT>
187 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectCntImm()
271 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
273 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm);
318 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64); in SelectInlineAsmMemoryOperand()
355 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32); in SelectArithImmed()
356 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32); in SelectArithImmed()
381 if (N.getValueType() == MVT::i32) in SelectNegArithImmed()
389 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val, in SelectNegArithImmed()
[all …]
DAArch64FastISel.cpp182 bool isTypeLegal(Type *Ty, MVT &VT);
183 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
187 bool simplifyAddress(Address &Addr, MVT VT);
196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc9 bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
10 MVT LocVT, CCValAssign::LocInfo LocInfo,
12 bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
15 bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
18 bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
21 bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
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DAArch64GenFastISel.inc97 unsigned fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(MVT RetVT) {
98 if (RetVT.SimpleTy != MVT::i64)
103 unsigned fastEmit_AArch64ISD_THREAD_POINTER_(MVT VT, MVT RetVT) {
105 case MVT::i64: return fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(RetVT);
112 unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
121 unsigned fastEmit_AArch64ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
122 if (RetVT.SimpleTy != MVT::isVoid)
127 unsigned fastEmit_AArch64ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
129 case MVT::i64: return fastEmit_AArch64ISD_CALL_MVT_i64_r(RetVT, Op0, Op0IsKill);
136 unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc66 /* 21*/ OPC_CheckChild1Type, MVT::i32,
69 /* 26*/ OPC_CheckChild1Type, MVT::i32,
77 /* 41*/ OPC_CheckChild1Type, MVT::i32,
80 /* 45*/ OPC_CheckType, MVT::i32,
83 /* 51*/ OPC_EmitInteger, MVT::i32, 14,
84 /* 54*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
86 MVT::i32, 3/*#Ops*/, 0, 1, 2,
91 /* 69*/ OPC_EmitInteger, MVT::i32, 14,
92 /* 72*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
94 MVT::i32, 3/*#Ops*/, 0, 1, 2,
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DARMGenCallingConv.inc9 bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
10 MVT LocVT, CCValAssign::LocInfo LocInfo,
12 static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
15 bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
18 bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
21 bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
[all …]
DARMGenFastISel.inc80 unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
81 if (RetVT.SimpleTy != MVT::isVoid)
89 unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
91 case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
98 unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
99 if (RetVT.SimpleTy != MVT::isVoid)
113 unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
115 case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
122 unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
123 if (RetVT.SimpleTy != MVT::isVoid)
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc65 /* 17*/ OPC_CheckChild0Type, MVT::v16i8,
66 /* 19*/ OPC_CheckType, MVT::i32,
77 /* 39*/ OPC_EmitInteger, MVT::i32, PPC::VSRCRegClassID,
79 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
94 /* 75*/ OPC_EmitInteger, MVT::i32, PPC::VSRCRegClassID,
96 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
103 /* 96*/ OPC_CheckChild0Type, MVT::v8i16,
104 /* 98*/ OPC_CheckType, MVT::i32,
115 /* 118*/ OPC_EmitInteger, MVT::i32, PPC::VSRCRegClassID,
117 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
[all …]
DPPCGenFastISel.inc32 unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
33 if (RetVT.SimpleTy != MVT::i64)
38 unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
40 case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
47 unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
48 if (RetVT.SimpleTy != MVT::f64)
56 unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
58 case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
65 unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
66 if (RetVT.SimpleTy != MVT::i32)
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DPPCGenCallingConv.inc9 bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT,
10 MVT LocVT, CCValAssign::LocInfo LocInfo,
12 bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
15 static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
18 bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
21 static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc9 static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
10 MVT LocVT, CCValAssign::LocInfo LocInfo,
12 bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
15 static bool CC_X86_32(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
18 static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
21 static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
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DX86GenFastISel.inc42 unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
43 if (RetVT.SimpleTy != MVT::v16i8)
57 unsigned fastEmit_ISD_ABS_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
58 if (RetVT.SimpleTy != MVT::v32i8)
69 unsigned fastEmit_ISD_ABS_MVT_v64i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
70 if (RetVT.SimpleTy != MVT::v64i8)
78 unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
79 if (RetVT.SimpleTy != MVT::v8i16)
93 unsigned fastEmit_ISD_ABS_MVT_v16i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
94 if (RetVT.SimpleTy != MVT::v16i16)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc55 unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
56 if (RetVT.SimpleTy != MVT::f32)
70 unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
71 if (RetVT.SimpleTy != MVT::f64)
79 unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
80 if (RetVT.SimpleTy != MVT::i32)
94 unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
95 if (RetVT.SimpleTy != MVT::i64)
103 unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
[all …]
DMipsGenCallingConv.inc9 static bool CC_Mips(unsigned ValNo, MVT ValVT,
10 MVT LocVT, CCValAssign::LocInfo LocInfo,
12 static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
15 static bool CC_MipsN(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
18 static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT,
19 MVT LocVT, CCValAssign::LocInfo LocInfo,
21 static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT,
22 MVT LocVT, CCValAssign::LocInfo LocInfo,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp16 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
17 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
18 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
19 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
25 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
26 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
27 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
28 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
29 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
30 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
[all …]
DHexagonISelLowering.cpp132 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
169 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
231 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
337 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
345 MVT::i32, Glue); in LowerCallResult()
354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
394 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
467 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
500 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
552 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp48 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
70 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
76 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
79 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
82 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
[all …]
DR600ISelLowering.cpp59 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
72 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
78 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp41 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
42 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
54 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
55 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
82 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
83 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
106 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
107 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
109 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
114 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
[all …]

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