| /third_party/ltp/tools/sparse/sparse-src/ |
| D | simplify.c | 704 case OP_AND: in eval_op()
784 if (and->opcode != OP_AND) in simplify_mask_or_and()
967 case OP_AND: in simplify_shift()
983 insn->opcode = OP_AND; in simplify_shift()
1004 case OP_AND: in simplify_shift()
1052 insn->opcode = OP_AND; in simplify_shift()
1112 case OP_AND: in simplify_seteq_setne()
1161 def->opcode = OP_AND; in simplify_seteq_setne()
1275 case OP_AND: in simplify_compare_constant()
1430 return replace_opcode(def, OP_AND); in simplify_compare_constant()
[all …]
|
| D | cse.c | 55 case OP_AND: case OP_OR: in cse_collect()
178 case OP_AND: case OP_OR: in insn_compare()
|
| D | linearize.c | 204 [OP_AND] = "and",
1014 ori = add_binary_op(ep, btype, OP_AND, ori, value_pseudo(~mask & smask)); in linearize_bitfield_insert()
1472 [SPECIAL_AND_ASSIGN - SPECIAL_BASE] = OP_AND, in linearize_assignment()
1573 int op = (expr->op == SPECIAL_LOGICAL_OR) ? OP_OR : OP_AND; in linearize_binop_bool()
1589 ['%'] = OP_MODU, ['&'] = OP_AND, in linearize_binop()
|
| D | scheck.c | 116 case OP_AND: t = boolector_and(btor, a, b); break; in binary()
|
| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_target_nvc0.cpp | 117 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
198 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN, in initOpInfo()
204 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN in initOpInfo()
494 case OP_AND: in isModSupported()
649 case OP_AND: in getThroughput()
|
| D | nv50_ir_target_nv50.cpp | 94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
116 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN, in initOpInfo()
366 if (ldSize == 2 && (i->op == OP_AND || i->op == OP_OR || i->op == OP_XOR)) in insnCanLoad()
479 case OP_AND: in isModSupported()
|
| D | nv50_ir_lowering_gv100.cpp | 131 case OP_AND: subOp = src0 & src1; break; in handleLOP2()
257 case OP_AND: in visit()
356 bld.mkOp2(OP_AND, TYPE_U32, mask, i->getSrc(0), mask); in handleEXTBF()
393 bld.mkOp2(OP_AND, TYPE_U32, src0, i->getSrc(0), mask); in handleINSBF()
|
| D | nv50_ir_lowering_nvc0.cpp | 1507 op = OP_AND; in handleSharedATOMNVE4()
1599 op = OP_AND; in handleSharedATOM()
1839 ptr = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(511)); in loadSuInfo32()
1841 ptr = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(7)); in loadSuInfo32()
1881 return bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), tmp, bld.mkImm(1)); in loadMsAdjInfo32()
1981 s = bld.mkOp2v(OP_AND, TYPE_U32, ts, s, bld.loadImm(NULL, 0x7)); in adjustCoordinatesMS()
2070 bld.mkOp2(OP_AND, TYPE_U32, off, src[0], bld.loadImm(NULL, 0xffff)); in processSurfaceCoordsNVE4()
2417 ptr = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(7)); in processSurfaceCoordsNVC0()
2447 bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), in processSurfaceCoordsNVC0()
2639 Value *is_3d = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), v, bld.mkImm(1)); in processSurfaceCoordsGM107()
[all …]
|
| D | nv50_ir_target_gm107.cpp | 214 case OP_AND: in getLatency()
|
| D | nv50_ir_peephole.cpp | 461 if (insn->op == OP_AND) { in findOriginForTestWithZero()
667 case OP_AND: in expr()
1301 i->op = OP_AND; in opnd()
1316 Value *mod = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), abs, in opnd()
1397 case OP_AND: in opnd()
1487 i->op = OP_AND; in opnd()
2032 if ((logop->op == OP_AND || logop->op == OP_OR) && in handleLOGOP()
2051 operation redOp = (logop->op == OP_AND ? OP_SET_AND : in handleLOGOP()
2195 } else if (insn->op == OP_AND) { in handleCVT_EXTBF()
2316 if (isFloatType(i->sType) || !src || src->op != OP_AND) in handleNEG()
[all …]
|
| D | nv50_ir_lowering_nv50.cpp | 1306 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x0000ffff)); in handleRDSV()
1308 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x03ff0000)); in handleRDSV()
1524 op = OP_AND; in handleSharedATOM()
1635 bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), in handleMEMBAR()
1786 coord_in_tile[i] = bld.mkOp2v(OP_AND, TYPE_U16, bld.getSSA(2), coords[i], tile_mask[i]); in processSurfaceCoords()
2079 …bld.mkOp2(OP_AND, TYPE_U16, untypedDst16[i], untypedDst16[i], bld.loadImm(NULL, (uint16_t)((1 << f… in handleSUSTP()
2095 … bld.mkOp2(OP_AND, TYPE_U16, untypedDst16[i], untypedDst16[i], bld.loadImm(NULL, (uint16_t)0xff)); in handleSUSTP()
|
| D | nv50_ir_lowering_helper.cpp | 48 case OP_AND: in visit()
|
| D | nv50_ir_lowering_gm107.cpp | 276 Value *tmp = bld.mkOp2v(OP_AND, i->sType, bld.getScratch(), in handlePOPCNT()
|
| D | nv50_ir_emit_nv50.cpp | 1612 assert(i->op == OP_AND); in emitLogicOp()
1621 case OP_AND: code[1] = 0x00000000; break; in emitLogicOp()
2006 case OP_AND: in emitInstruction()
|
| /third_party/flutter/skia/third_party/externals/angle2/src/tests/preprocessor_tests/ |
| D | operator_test.cpp | 62 {"&&", pp::Token::OP_AND},
|
| /third_party/skia/third_party/externals/angle2/src/tests/preprocessor_tests/ |
| D | operator_test.cpp | 62 {"&&", pp::Token::OP_AND},
|
| /third_party/skia/third_party/externals/angle2/src/compiler/preprocessor/ |
| D | Token.h | 42 OP_AND, enumerator
|
| D | preprocessor.y | 372 case angle::pp::Token::OP_AND:
|
| D | preprocessor.l | 204 return angle::pp::Token::OP_AND;
|
| /third_party/flutter/skia/third_party/externals/angle2/src/compiler/preprocessor/ |
| D | Token.h | 42 OP_AND, enumerator
|
| D | ExpressionParser.y | 370 case angle::pp::Token::OP_AND:
|
| D | Tokenizer.l | 196 return angle::pp::Token::OP_AND;
|
| /third_party/skia/third_party/externals/swiftshader/src/OpenGL/compiler/preprocessor/ |
| D | Token.h | 47 OP_AND, enumerator
|
| D | ExpressionParser.y | 384 case pp::Token::OP_AND:
|
| D | Tokenizer.l | 204 return pp::Token::OP_AND;
|