Searched refs:OP_SET_AND (Results 1 – 13 of 13) sorted by relevance
| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_inlines.h | 286 if (op >= OP_SET_AND && op <= OP_SLCT && op != OP_SELP) in asCmp()
293 if (op >= OP_SET_AND && op <= OP_SLCT && op != OP_SELP) in asCmp()
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| D | nv50_ir_target_gv100.cpp | 36 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT in initOpInfo()
344 case OP_SET_AND: in getOpInfo()
451 op == OP_SET_AND || in isOpSupported()
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| D | nv50_ir_target_gm107.cpp | 230 case OP_SET_AND: in getLatency()
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| D | nv50_ir_target_nv50.cpp | 117 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT in initOpInfo()
446 case OP_SET_AND: in isOpSupported()
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| D | nv50_ir_emit_gv100.cpp | 521 case OP_SET_AND: emitField(74, 2, 0); break; in emitFSET_BF()
546 case OP_SET_AND: emitField(74, 2, 0); break; in emitFSETP()
648 case OP_SET_AND: emitField(74, 2, 0); break; in emitDSETP()
741 case OP_SET_AND: emitField(74, 2, 0); break; in emitISETP()
1952 case OP_SET_AND: in emitInstruction()
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| D | nv50_ir_target_nvc0.cpp | 141 { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
199 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT in initOpInfo()
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| D | nv50_ir_emit_gm107.cpp | 1212 case OP_SET_AND: emitField(0x2d, 2, 0); break; in emitDSET()
1260 case OP_SET_AND: emitField(0x2d, 2, 0); break; in emitDSETP()
1599 case OP_SET_AND: emitField(0x2d, 2, 0); break; in emitFSET()
1648 case OP_SET_AND: emitField(0x2d, 2, 0); break; in emitFSETP()
2098 case OP_SET_AND: emitField(0x2d, 2, 0); break; in emitISET()
2144 case OP_SET_AND: emitField(0x2d, 2, 0); break; in emitISETP()
3588 case OP_SET_AND: in emitInstruction()
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| D | nv50_ir_lowering_gv100.cpp | 271 case OP_SET_AND: in visit()
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| D | nv50_ir_peephole.cpp | 237 if (insn->op == OP_SET || insn->op == OP_SET_AND || in checkSwapSrc01()
2051 operation redOp = (logop->op == OP_AND ? OP_SET_AND : in handleLOGOP()
2056 set0->op != OP_SET_AND && in handleLOGOP()
2330 if ((set->op == OP_SET || set->op == OP_SET_AND || in handleNEG()
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| D | nv50_ir.h | 81 OP_SET_AND, // dst = (src0 CMP src1) & src2 enumerator
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| D | nv50_ir_emit_gk110.cpp | 1173 case OP_SET_AND: code[1] |= 0x0 << 16; break; in emitSET()
2605 case OP_SET_AND: in emitInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 1188 case OP_SET_AND: hi = 0x10000000; break; in emitSET()
2775 case OP_SET_AND: in emitInstruction()
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| D | nv50_ir_lowering_nvc0.cpp | 359 case OP_SET_AND: in visit()
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