| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1723 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1724 if (OpReg == 0) return false; in X86SelectBranch()
1727 .addReg(OpReg).addImm(1); in X86SelectBranch()
1758 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1759 if (OpReg == 0) return false; in X86SelectBranch()
1762 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1763 unsigned KOpReg = OpReg; in X86SelectBranch()
1764 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1766 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1768 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Kill=*/true, in X86SelectBranch()
[all …]
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| D | X86SpeculativeLoadHardening.cpp | 2034 Register OpReg = Op->getReg(); in hardenLoadAddr() local
2035 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
2073 .addReg(OpReg); in hardenLoadAddr()
2104 .addReg(OpReg); in hardenLoadAddr()
2117 .addReg(OpReg); in hardenLoadAddr()
2126 .addReg(OpReg) in hardenLoadAddr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 298 Register OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
300 if (!Register::isVirtualRegister(OpReg)) in optimizeSDPattern()
303 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
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| D | ARMInstructionSelector.cpp | 1045 Register OpReg = I.getOperand(2).getReg(); in select() local
1046 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
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| D | ARMFastISel.cpp | 1276 unsigned OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1277 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1280 .addReg(OpReg).addImm(1)); in SelectBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 163 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister() argument
166 if (encodeOperand(OpReg, Reg, WantedRegSet) != true) in encodeRegister()
172 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
174 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
177 IValueT encodeFPRegister(const Operand *OpReg, const char *RegName, in encodeFPRegister() argument
179 return encodeRegister(OpReg, WantFPRegs, RegName, InstName); in encodeFPRegister()
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| D | IceAssemblerARM32.cpp | 540 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister() argument
543 if (encodeOperand(OpReg, Reg, WantedRegSet) != EncodedAsRegister) in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
551 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister() argument
556 return encodeRegister(OpReg, WantSRegs, RegName, InstName); in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister() argument
561 return encodeRegister(OpReg, WantDRegs, RegName, InstName); in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister() argument
566 return encodeRegister(OpReg, WantQRegs, RegName, InstName); in encodeQRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3515 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
3517 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
3524 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarExtract()
3582 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
3584 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
3592 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
3595 DstRegs.push_back(OpReg); in narrowScalarInsert()
3614 Register SegReg = OpReg; in narrowScalarInsert()
3618 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalarInsert()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1711 unsigned OpReg = getRegForValue(In); in selectFNeg() local
1712 if (!OpReg) in selectFNeg()
1719 OpReg, OpRegIsKill); in selectFNeg()
1734 ISD::BITCAST, OpReg, OpRegIsKill); in selectFNeg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1858 Register OpReg = MO.getReg(); in clearRegisterKills() local
1859 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86InstComments.cpp | 217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
218 return getVectorRegSize(OpReg) / ScalarSize; in getRegOperandNumElts()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 2326 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
2327 unsigned Size = getSizeInBits(OpReg, MRI, *TRI); in getImageMapping()
2337 unsigned NewBank = getRegBankID(OpReg, MRI, *TRI, AMDGPU::SGPRRegBankID); in getImageMapping()
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| D | SIInstrInfo.cpp | 4287 Register OpReg = Op.getReg(); in legalizeGenericOperand() local
4291 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
4304 MachineInstr *Def = MRI.getVRegDef(OpReg); in legalizeGenericOperand()
4310 FoldImmediate(*Copy, *Def, OpReg, &MRI); in legalizeGenericOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4513 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4530 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
5259 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5263 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5264 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5269 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 7181 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
7182 if (OpReg == Reg) in checkLowRegisterList()
7185 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
7195 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
7196 if (OpReg == Reg) in listContainsReg()
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