| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.h | 75 void emitRsRt(IValueT Opcode, const Operand *OpRs, const Operand *OpRt,
78 void emitRtRsImm16(IValueT Opcode, const Operand *OpRt, const Operand *OpRs,
81 void emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt,
82 const Operand *OpRs, const Operand *OpImm,
85 void emitFtRsImm16(IValueT Opcode, const Operand *OpFt, const Operand *OpRs,
88 void emitRdRtSa(IValueT Opcode, const Operand *OpRd, const Operand *OpRt,
91 void emitRdRsRt(IValueT Opcode, const Operand *OpRd, const Operand *OpRs,
92 const Operand *OpRt, const char *InsnName);
95 const Operand *OpFs, const Operand *OpFt, IValueT CC,
99 const Operand *OpFd, const Operand *OpFs,
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| D | IceAssemblerARM32.h | 176 void adc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
179 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
182 void and_(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
185 void asr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
192 void bic(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
197 void blx(const Operand *Target);
201 void clz(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
203 void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
205 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
209 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
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| D | IceAssemblerMIPS32.cpp | 143 bool encodeOperand(const Operand *Opnd, IValueT &Value, in encodeOperand()
163 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister()
172 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister()
177 IValueT encodeFPRegister(const Operand *OpReg, const char *RegName, in encodeFPRegister()
207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt()
208 const Operand *OpRt, const char *InsnName) { in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16()
219 const Operand *OpRs, const uint32_t Imm, in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel()
232 const Operand *OpRs, in emitRtRsImm16Rel()
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| D | IceTargetLoweringX8632.h | 92 const Inst *getProducerFor(const Operand *Opnd) const;
248 Operand *loOperand(Operand *Operand);
249 Operand *hiOperand(Operand *Operand);
257 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
304 Operand *Addr);
310 void doMockBoundsCheck(Operand *Opnd) override;
313 void lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr, Operand *Expected,
314 Operand *Desired);
316 bool tryOptimizedCmpxchgCmpBr(Variable *DestPrev, Operand *Ptr,
317 Operand *Expected, Operand *Desired);
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| D | IceTargetLoweringX8664.h | 93 const Inst *getProducerFor(const Operand *Opnd) const;
253 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
300 Operand *Addr);
306 void doMockBoundsCheck(Operand *Opnd) override;
309 void lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr, Operand *Expected,
310 Operand *Desired);
312 bool tryOptimizedCmpxchgCmpBr(Variable *DestPrev, Operand *Ptr,
313 Operand *Expected, Operand *Desired);
314 void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
315 Operand *Val);
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| D | IceAssemblerARM32.cpp | 352 EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value, in encodeOperand()
388 Operand *Amt = FlexReg->getShiftAmt(); in encodeOperand()
480 EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value, in encodeAddress()
540 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister()
816 const Operand *OpRd, const Operand *OpRn, in emitType01()
817 const Operand *OpSrc1, bool SetFlags, in emitType01()
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| D | IceInstX8632.h | 56 class X86Operand : public ::Ice::Operand {
62 enum OperandKindX8632 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
63 using ::Ice::Operand::dump;
69 : Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {} in X86Operand()
126 static bool classof(const Operand *Operand) { in classof() argument
127 return Operand->getKind() == static_cast<OperandKind>(kMem); in classof()
167 static bool classof(const Operand *Operand) { in classof() argument
168 return Operand->getKind() == static_cast<OperandKind>(kSplit); in classof()
360 static void validateVectorAddrModeOpnd(const Operand *Opnd) { in validateVectorAddrModeOpnd()
379 static InstX86FakeRMW *create(Cfg *Func, Operand *Data, Operand *Addr,
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| D | IceInstX8664.h | 55 class X86Operand : public ::Ice::Operand {
61 enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
62 using ::Ice::Operand::dump;
68 : Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {} in X86Operand()
110 static bool classof(const Operand *Operand) { in classof() argument
111 return Operand->getKind() == static_cast<OperandKind>(kMem); in classof()
299 static void validateVectorAddrModeOpnd(const Operand *Opnd) { in validateVectorAddrModeOpnd()
318 static InstX86FakeRMW *create(Cfg *Func, Operand *Data, Operand *Addr,
326 Operand *getAddr() const { return this->getSrc(1); } in getAddr()
327 Operand *getData() const { return this->getSrc(0); } in getData()
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| /third_party/spirv-tools/utils/vscode/src/schema/ |
| D | schema.go | 25 Operands []Operand
29 type Operand struct { struct
956 Operands: []Operand {
963 Operands: []Operand {
964 Operand {
969 Operand {
980 Operands: []Operand {
981 Operand {
992 Operands: []Operand {
993 Operand {
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| /third_party/skia/third_party/externals/spirv-tools/utils/vscode/src/schema/ |
| D | schema.go | 25 Operands []Operand
29 type Operand struct { struct
956 Operands: []Operand {
963 Operands: []Operand {
964 Operand {
969 Operand {
980 Operands: []Operand {
981 Operand {
992 Operands: []Operand {
993 Operand {
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/utils/vscode/src/schema/ |
| D | schema.go | 25 Operands []Operand
29 type Operand struct { struct
956 Operands: []Operand {
963 Operands: []Operand {
964 Operand {
969 Operand {
980 Operands: []Operand {
981 Operand {
992 Operands: []Operand {
993 Operand {
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| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_to_hw_instr.cpp | 54 bld.pseudo(aco_opcode::p_unit_test, Operand::zero());
57 Operand(v1_lo, v2b), Operand(v0_lo, v2b));
63 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(1u));
66 Operand(v1_lo, v2b), Operand(v0_lo, v2b));
73 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(2u));
75 Definition(v0_lo, v6b), Operand(v1_lo, v2b),
76 Operand(v0_lo, v2b), Operand(v2_lo, v2b));
84 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(3u));
87 Operand(v1_lo, v2b), Operand(v0_lo, v2b),
88 Operand(v2_lo, v2b), Operand(v3_lo, v2b));
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| D | test_sdwa.cpp | 80 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]);
81 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u));
86 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]);
87 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u));
171 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
172 Operand::c32(is_signed));
176 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u),
177 Operand::c32(is_signed));
181 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u),
182 Operand::c32(is_signed));
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| D | test_optimizer_postRA.cpp | 51 auto vcmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), Operand::zero(),
52 Operand(v_in, reg_v0));
53 …2(Builder::s_and, bld.def(bld.lm, reg_s0), bld.def(s1, scc), bld.vcc(vcmp), Operand(exec, bld.lm));
55 writeout(0, Operand(br, reg_s2));
68 auto vcmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), Operand::zero(),
69 Operand(v_in, reg_v0));
70 …2(Builder::s_and, bld.def(bld.lm, reg_s0), bld.def(s1, scc), bld.vcc(vcmp), Operand(exec, bld.lm));
71 auto ovrwr = bld.sop1(Builder::s_mov, bld.def(bld.lm, vcc), Operand::zero());
73 writeout(1, Operand(br, reg_s2), Operand(ovrwr, vcc));
85 auto vcmp = bld.vopc_e64(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, reg_s4), Operand::zero(),
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| D | test_hard_clause.cpp | 31 Operand desc_op(desc); in create_mubuf()
34 Operand(PhysReg(256), v1), Operand::zero(), 0, false) in create_mubuf()
41 bld.mubuf(aco_opcode::buffer_store_dword, Operand(PhysReg(0), s4), Operand(PhysReg(256), v1), in create_mubuf_store()
42 Operand(PhysReg(256), v1), Operand::zero(), 0, false); in create_mubuf_store()
47 Operand desc_op(desc); in create_mtbuf()
50 Operand(PhysReg(256), v1), Operand::zero(), V_008F0C_BUF_DATA_FORMAT_32, in create_mtbuf()
59 Operand(PhysReg(256), v2), Operand(s2)); in create_flat()
65 Operand(PhysReg(256), v2), Operand(s2)); in create_global()
73 mimg->operands[0] = Operand(desc); in create_mimg()
75 mimg->operands[1] = Operand(PhysReg(0), s4); in create_mimg()
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| D | test_insert_nops.cpp | 30 bld.mubuf(aco_opcode::buffer_load_dword, Definition(PhysReg(256), v1), Operand(PhysReg(0), s4), in create_mubuf()
31 Operand(PhysReg(256), v1), Operand::zero(), offset, true); in create_mubuf()
39 mimg->operands[0] = Operand(PhysReg(0), s8); in create_mimg()
40 mimg->operands[1] = Operand(PhysReg(0), s4); in create_mimg()
41 mimg->operands[2] = Operand(v1); in create_mimg()
43 mimg->operands[3 + i] = Operand(PhysReg(256 + (nsa ? i * 2 : i)), v1); in create_mimg()
60 bld.pseudo(aco_opcode::p_unit_test, Operand::zero());
69 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(1u));
77 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(2u));
86 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(3u));
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| D | test_optimizer.cpp | 44 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x123456u), neg_a));
100 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x3f000000u), tmp));
105 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x40000000u), tmp));
110 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x40800000u), tmp));
115 writeout(3, bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), Operand::zero(),
116 Operand::c32(0x3f800000u), tmp));
121 tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x40000000u), tmp);
122 writeout(4, bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), Operand::zero(),
123 Operand::c32(0x3f800000u), tmp));
130 writeout(5, bld.vop2(aco_opcode::v_mul_f16, bld.def(v2b), Operand::c16(0x3800u), tmp));
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 18 // Operand: wd
21 // Operand: ws
24 // Operand: wt
34 // Operand: wd
37 // Operand: ws
40 // Operand: wt
50 // Operand: wd
53 // Operand: ws
56 // Operand: wt
66 // Operand: rs
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 18 // Operand: target
21 // Operand: p
31 // Operand: wb
34 // Operand: Rn
37 // Operand: p
42 // Operand: regs
56 // Operand: Rd
59 // Operand: Rn
62 // Operand: Rm
65 // Operand: Ra
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| /third_party/skia/third_party/externals/tint/src/writer/spirv/ |
| D | builder.cc | 306 {Operand::Int(SpvAddressingModelLogical), in Build()
307 Operand::Int(SpvMemoryModelGLSL450)}); in Build()
324 Operand Builder::result_op() { in result_op()
325 return Operand::Int(next_id()); in result_op()
385 Instruction{spv::Op::OpCapability, {Operand::Int(cap)}}); in push_capability()
390 if (!push_function_inst(spv::Op::OpLabel, {Operand::Int(id)})) { in GenerateLabel()
428 {Operand::Int(merge_stack_.back())})) { in GenerateBreakStatement()
440 {Operand::Int(continue_stack_.back())})) { in GenerateContinueStatement()
464 Operand::Int(stage), Operand::Int(id), in GenerateEntryPoint()
465 Operand::String(builder_.Symbols().NameFor(func->symbol))}; in GenerateEntryPoint()
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| D | operand.cc | 22 Operand Operand::Float(float val) { in Float()
23 Operand o(Kind::kFloat); in Float()
29 Operand Operand::Int(uint32_t val) { in Int()
30 Operand o(Kind::kInt); in Int()
36 Operand Operand::String(const std::string& val) { in String()
37 Operand o(Kind::kString); in String()
42 Operand::Operand(Kind kind) : kind_(kind) {} in Operand() function in tint::writer::spirv::Operand
44 Operand::~Operand() = default;
46 uint32_t Operand::length() const { in length()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 189 emit_vadd32(Builder& bld, Definition def, Operand src0, Operand src1) in emit_vadd32()
191 Instruction* instr = bld.vadd32(def, src0, src1, false, Operand(s2), true); in emit_vadd32()
201 unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL) in emit_int64_dpp_op()
206 Operand src0[] = {Operand(src0_reg, v1), Operand(PhysReg{src0_reg + 1}, v1)}; in emit_int64_dpp_op()
207 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; in emit_int64_dpp_op()
208 Operand src1_64 = Operand(src1_reg, v2); in emit_int64_dpp_op()
209 Operand vtmp_op[] = {Operand(vtmp_reg, v1), Operand(PhysReg{vtmp_reg + 1}, v1)}; in emit_int64_dpp_op()
210 Operand vtmp_op64 = Operand(vtmp_reg, v2); in emit_int64_dpp_op()
223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
259 bld.vop2(aco_opcode::v_cndmask_b32, dst[0], vtmp_op[0], src1[0], Operand(vcc, bld.lm)); in emit_int64_dpp_op()
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| /third_party/skia/third_party/externals/swiftshader/src/Pipeline/ |
| D | SpirvShaderGLSLstd450.cpp | 60 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
69 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
78 auto lhs = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
79 auto rhs = Operand(this, state, insn.word(6)); in EmitExtGLSLstd450()
87 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
96 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
105 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
114 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
123 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
132 auto src = Operand(this, state, insn.word(5)); in EmitExtGLSLstd450()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/DWARF/ |
| D | DWARFExpression.cpp | 133 for (unsigned Operand = 0; Operand < 2; ++Operand) { in extract() local
134 unsigned Size = Desc.Op[Operand]; in extract()
142 Operands[Operand] = Data.getU8(&Offset); in extract()
144 Operands[Operand] = (int8_t)Operands[Operand]; in extract()
147 Operands[Operand] = Data.getU16(&Offset); in extract()
149 Operands[Operand] = (int16_t)Operands[Operand]; in extract()
152 Operands[Operand] = Data.getU32(&Offset); in extract()
154 Operands[Operand] = (int32_t)Operands[Operand]; in extract()
157 Operands[Operand] = Data.getU64(&Offset); in extract()
161 Operands[Operand] = Data.getU64(&Offset); in extract()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonDepOperands.td | 17 def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDec…
20 def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3Imm…
23 def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedIm…
26 def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtarget…
29 def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsigned…
32 def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDec…
35 def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsigned…
38 def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedIm…
41 def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedIm…
44 def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brta…
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