Searched refs:PIPE_CONTROL_DATA_CACHE_FLUSH (Results 1 – 12 of 12) sorted by relevance
218 PIPE_CONTROL_DATA_CACHE_FLUSH), in iris_emit_buffer_barrier_for()223 [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH, in iris_emit_buffer_barrier_for()341 PIPE_CONTROL_DATA_CACHE_FLUSH | in iris_flush_all_caches()386 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL; in iris_memory_barrier()
71 PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_fine_fence_new()
144 { .iris = PIPE_CONTROL_DATA_CACHE_FLUSH, .ds = INTEL_DS_DATA_CACHE_FLUSH_BIT, }, in iris_utrace_pipe_flush_bit_to_ds_stall_flag()
351 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), enumerator365 PIPE_CONTROL_DATA_CACHE_FLUSH | \
265 PIPE_CONTROL_DATA_CACHE_FLUSH : 0) | in fast_clear_color()
414 PIPE_CONTROL_DATA_CACHE_FLUSH); in flush_before_state_base_change()656 PIPE_CONTROL_DATA_CACHE_FLUSH | in emit_pipeline_select()7635 if (flags & (PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_DATA_CACHE_FLUSH)) { in batch_mark_sync_for_pipe_control()7640 if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH)) { in batch_mark_sync_for_pipe_control()7664 if (flags & (PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_DATA_CACHE_FLUSH)) in batch_mark_sync_for_pipe_control()8028 PIPE_CONTROL_DATA_CACHE_FLUSH)))) { in iris_emit_raw_pipe_control()8095 PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_emit_raw_pipe_control()8121 (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "", in iris_emit_raw_pipe_control()8163 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH; in iris_emit_raw_pipe_control()
218 PIPE_CONTROL_DATA_CACHE_FLUSH | in crocus_emit_mi_flush()285 PIPE_CONTROL_DATA_CACHE_FLUSH | in crocus_flush_all_caches()335 unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL; in crocus_memory_barrier()
77 PIPE_CONTROL_DATA_CACHE_FLUSH; in crocus_fine_fence_new()
253 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), enumerator264 PIPE_CONTROL_DATA_CACHE_FLUSH | \
125 PIPE_CONTROL_DATA_CACHE_FLUSH |
431 GFX_VER >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; in flush_before_state_base_change()1083 PIPE_CONTROL_DATA_CACHE_FLUSH | in setup_l3_config()1110 PIPE_CONTROL_DATA_CACHE_FLUSH | in setup_l3_config()1250 GFX_VER >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; in emit_pipeline_select()8735 PIPE_CONTROL_DATA_CACHE_FLUSH))) {8828 PIPE_CONTROL_DATA_CACHE_FLUSH;8845 (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "",8867 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
1846 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH; in crocus_flush_bits_for_history()