Searched refs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 – 7 of 7) sorted by relevance
147 { .iris = PIPE_CONTROL_STATE_CACHE_INVALIDATE, .ds = INTEL_DS_STATE_CACHE_INVALIDATE_BIT, }, in iris_utrace_pipe_flush_bit_to_ds_stall_flag()
354 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator371 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
349 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in iris_flush_all_caches()
467 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in flush_after_state_base_change()663 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in emit_pipeline_select()4899 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in surf_state_update_clear_value()7911 if (GFX_VER <= 8 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { in iris_emit_raw_pipe_control()8125 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "", in iris_emit_raw_pipe_control()8175 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE; in iris_emit_raw_pipe_control()
292 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in crocus_flush_all_caches()
256 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator268 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
486 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in flush_after_state_base_change()1104 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in setup_l3_config()1262 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in emit_pipeline_select()6813 PIPE_CONTROL_STATE_CACHE_INVALIDATE);8608 if (GFX_VER >= 7 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) {8848 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "",8881 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE;