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Searched refs:PKT3_SET_SH_REG_INDEX (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_cs.h122 unsigned opcode = PKT3_SET_SH_REG_INDEX; in radeon_set_sh_reg_idx()
137 radeon_emit(cs, PKT3(PKT3_SET_SH_REG_INDEX, 1, 0)); in gfx10_set_sh_reg_idx3()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pm4.c111 si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG_INDEX, 3); in si_pm4_set_reg_idx3()
Dsi_build_pm4.h123 radeon_emit(PKT3(PKT3_SET_SH_REG_INDEX, num, 0)); \
/third_party/mesa3d/src/amd/common/
Dsid.h250 #define PKT3_SET_SH_REG_INDEX 0x9B macro
Dac_debug.c276 op == PKT3_SET_UCONFIG_REG_INDEX || op == PKT3_SET_SH_REG || op == PKT3_SET_SH_REG_INDEX) in ac_parse_packet3()
296 case PKT3_SET_SH_REG_INDEX: in ac_parse_packet3()
/third_party/libdrm/tests/amdgpu/
Dbasic_tests.c295 #define PKT3_SET_SH_REG_INDEX 0x9B macro
2591 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2); in amdgpu_dispatch_write_cumask()
2596 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2); in amdgpu_dispatch_write_cumask()
3546 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1); in amdgpu_draw_vs_RectPosTexFast_write2hw()
3550 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1); in amdgpu_draw_vs_RectPosTexFast_write2hw()
3656 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1); in amdgpu_draw_ps_write2hw()
3660 ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1); in amdgpu_draw_ps_write2hw()