Searched refs:PredOp (Results 1 – 4 of 4) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 215 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
226 const MachineOperand &PredOp, bool Cond,
625 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
857 const MachineOperand &PredOp, bool Cond, in predicateAt() argument
886 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, in predicateAt()
887 PredOp.getSubReg()); in predicateAt()
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| D | HexagonGenMux.cpp | 245 MachineOperand &PredOp = MI->getOperand(1); in genMuxInBlock() local
246 if (PredOp.isUndef()) in genMuxInBlock()
249 Register PR = PredOp.getReg(); in genMuxInBlock()
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| D | HexagonISelLowering.cpp | 925 SDValue PredOp = Op.getOperand(0); in LowerVSELECT() local
937 DAG.getSelect(dl, WideTy, PredOp, in LowerVSELECT()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MVETailPredication.cpp | 519 unsigned PredOp = ID == Intrinsic::masked_load ? 2 : 3; in TryConvert() local
520 auto *Predicate = dyn_cast<Instruction>(I->getArgOperand(PredOp)); in TryConvert()
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