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Searched refs:R31 (Results 1 – 25 of 31) sorted by relevance

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/third_party/openssl/crypto/sha/asm/
Dkeccak1600-avx512vl.pl56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
99 vprolvq $R31,$A31,$A31
212 vmovdqa64 2*32(%r8),$R31
298 vmovdqa64 2*32(%r8),$R31
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td75 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
89 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
118 R30, R31, R26, R27,
136 R30, R31, R26, R27,
DAVRISelLowering.cpp2024 .Case("r30", AVR::R30).Case("r31", AVR::R31) in getRegisterByName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
182 Defs = [PC, R31, R6, R7, P0] in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonRegisterInfo.cpp45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
140 Reserved.set(Hexagon::R31); in getReservedRegs()
290 return Hexagon::R31; in getRARegister()
DHexagonRegisterInfo.td94 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
113 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
338 R10, R11, R29, R30, R31)>;
DHexagonISelLowering.cpp274 .Case("r31", Hexagon::R31) in getRegisterByName()
293 .Case("lr", Hexagon::R31) in getRegisterByName()
DHexagonInstrInfo.cpp3816 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)) in getDuplexCandidateGroup()
3833 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))) in getDuplexCandidateGroup()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h111 case Lanai::R31: in getLanaiRegisterNumbering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp280 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup()
300 (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
635 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
638 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
DHexagonMCTargetDesc.cpp218 InitHexagonMCRegisterInfo(X, Hexagon::R31); in createHexagonMCRegisterInfo()
DHexagonMCChecker.cpp103 if (Hexagon::R31 != R && MCID.isCall()) in init()
DHexagonMCInstrInfo.cpp601 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31); in isIntReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc138 R31 = 118,
1266 { PPC::R31 },
1346 …PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, …
1356 …PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, …
1366 …PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, …
1922 { 31U, PPC::R31 },
2210 { 31U, PPC::R31 },
2434 { PPC::R31, -2U },
2709 { PPC::R31, 31U },
2987 { PPC::R31, -2U },
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp117 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
153 {PPC::R31, -4}, in getCalleeSavedSpillSlots()
560 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; in replaceFPWithRealFP()
833 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitPrologue()
1404 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitEpilogue()
1813 SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31); in determineCalleeSaves()
1867 unsigned MinGPR = PPC::R31; in processFunctionBeforeFrameFinalized()
DPPCCallingConv.td288 R29, R30, R31, F14, F15, F16, F17, F18,
298 R28, R29, R30, R31, CR2, CR3, CR4
314 R29, R30, R31, F14, F15, F16, F17, F18,
DPPCRegisterInfo.cpp324 markSuperRegs(Reserved, PPC::R31); in getReservedRegs()
538 .addReg(PPC::R31) in lowerDynamicAlloc()
1168 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; in getFrameRegister()
DPPCRegisterInfo.td258 R31, R0, R1, FP, BP)> {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp161 Lanai::R30, Lanai::R31};
/third_party/typescript/tests/cases/conformance/types/tuple/
DvariadicTuples1.ts293 type R31 = DropLast<readonly [symbol, string]>; alias
/third_party/typescript/tests/baselines/reference/
DvariadicTuples1.js291 type R31 = DropLast<readonly [symbol, string]>;
742 declare type R31 = DropLast<readonly [symbol, string]>;
DvariadicTuples1.symbols985 type R31 = DropLast<readonly [symbol, string]>;
986 >R31 : Symbol(R31, Decl(variadicTuples1.ts, 288, 55))
DvariadicTuples1.types980 type R31 = DropLast<readonly [symbol, string]>;
981 >R31 : [symbol]
DvariadicTuples1.errors.txt400 type R31 = DropLast<readonly [symbol, string]>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp547 Hexagon::R30, Hexagon::R31}; in DecodeIntRegsRegisterClass()

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