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Searched refs:R_028644_SPI_PS_INPUT_CNTL_0 (Results 1 – 7 of 7) sorted by relevance

/third_party/mesa3d/src/amd/common/
Dac_shadowed_regs.c96 R_028644_SPI_PS_INPUT_CNTL_0,
97 R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
307 R_028644_SPI_PS_INPUT_CNTL_0,
308 R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
648 R_028644_SPI_PS_INPUT_CNTL_0,
649 R_028714_SPI_SHADER_COL_FORMAT - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
967 R_028644_SPI_PS_INPUT_CNTL_0,
968 R_0286F0_SPI_GFX_SCRATCH_BASE_HI - R_028644_SPI_PS_INPUT_CNTL_0 + 4,
1946 set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Gfx9)); in gfx9_emulate_clear_state()
2653 set_context_reg_seq_array(cs, R_028644_SPI_PS_INPUT_CNTL_0, SET(SpiPsInputCntl0Nv10)); in gfx10_emulate_clear_state()
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/third_party/mesa3d/src/gallium/drivers/r600/
Dr600d.h1512 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
2423 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
Devergreend.h1827 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 macro
Dr600_state.c2462 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput); in r600_update_ps_state()
Devergreen_state.c3407 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num); in evergreen_update_ps_state()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp105 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl, in si_emit_spi_map()
/third_party/mesa3d/src/amd/vulkan/
Dradv_pipeline.c6341 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset); in radv_pipeline_emit_ps_inputs()