| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
93 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
97 __ xchg(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
99 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
108 ASSERT_EQ(V1, test.Reg0()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
119 if (GPRRegister::Encoded_Reg_##Reg0 < 4 && \ in TEST_F()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 119 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
123 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
125 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
137 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
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| D | MipsSEFrameLowering.cpp | 463 unsigned Reg0 = in emitPrologue() local
469 std::swap(Reg0, Reg1); in emitPrologue()
472 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
485 std::swap(Reg0, Reg1); in emitPrologue()
488 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
96 __ mov(IceType_i##Size, Encoded_GPR_##Reg0(), Immediate(Value0)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
99 __ And(IceType_i32, Encoded_GPR_##Reg0(), Immediate(Mask##Size)); \ in TEST_F()
106 ASSERT_EQ(V1, test.Reg0()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
170 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
187 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
210 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
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| D | MipsMCCodeEmitter.cpp | 98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
104 if (Reg0 < Reg1) in LowerCompactBranch()
107 if (Reg0 >= Reg1) in LowerCompactBranch()
111 if (Reg1 >= Reg0) in LowerCompactBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 240 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
241 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
245 if (Register::isVirtualRegister(Reg0)) { in runOnMachineFunction()
247 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
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| D | HexagonBitTracker.cpp | 316 unsigned Reg0 = Reg[0].Reg; in evaluate() local
842 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
844 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
846 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
848 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2063 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2085 Ops.push_back(Reg0); in SelectVLD()
2088 Ops.push_back(Reg0); in SelectVLD()
2101 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2114 Ops.push_back(Reg0); in SelectVLD()
2118 Ops.push_back(Reg0); in SelectVLD()
2195 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2242 Ops.push_back(Reg0); in SelectVST()
2246 Ops.push_back(Reg0); in SelectVST()
2271 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
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| D | Thumb2SizeReduction.cpp | 746 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
752 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
755 if (Reg0 != Reg2) { in ReduceTo2Addr()
758 if (Reg1 != Reg0) in ReduceTo2Addr()
765 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
770 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
777 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
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| D | ARMAsmPrinter.cpp | 312 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
313 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 739 uint16_t Reg0 = 0; variable
747 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
753 return Reg0;
758 return Reg0; in isValid()
764 Reg0 = Reg1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 174 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
196 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
199 Reg0 = Reg2; in commuteInstructionImpl()
201 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
204 Reg0 = Reg1; in commuteInstructionImpl()
218 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
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| D | RegisterCoalescer.cpp | 2502 unsigned Reg0; in valuesIdentical() local
2503 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2504 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2514 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2520 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1440 printRegName(O, Reg0); in printVectorListTwo()
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1453 printRegName(O, Reg0); in printVectorListTwoSpaced()
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1508 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1555 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 505 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
508 .addImm(Reg0) in InsertSEH()
518 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
520 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
526 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
556 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
559 .addImm(Reg0) in InsertSEH()
567 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
569 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
575 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.h | 566 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
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| D | AMDGPUBaseInfo.cpp | 968 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect() argument
969 for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) { in isRegIntersect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 2055 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); in EmitInstruction() local
2060 MIB.addReg(Reg0); in EmitInstruction()
2086 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); in EmitInstruction() local
2093 MIB.addReg(Reg0); in EmitInstruction()
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| D | X86InstrInfo.cpp | 4943 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
4953 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
4954 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 784 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP() argument
791 .addReg(Reg0) in buildEXP()
1133 Register Reg0 = I.getOperand(3).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
1140 MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, in selectG_INTRINSIC_W_SIDE_EFFECTS()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 395 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
405 if (Reg0 == Reg1) { in commuteInstructionImpl()
425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
428 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstX8632.cpp | 2784 const GPRRegister Reg0 = RegX8632::getEncodedGPR(VarReg0->getRegNum()); in emitIAS() local
2785 Asm->xchg(Ty, Reg0, Reg1); in emitIAS()
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| D | IceInstX8664.cpp | 2711 const GPRRegister Reg0 = RegX8664::getEncodedGPR(VarReg0->getRegNum()); in emitIAS() local
2712 Asm->xchg(Ty, Reg0, Reg1); in emitIAS()
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