| /third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 16 glm_uvec4 Reg1; in glm_i128_interleave() local
22 Reg1 = x; in glm_i128_interleave()
26 Reg2 = _mm_slli_si128(Reg1, 2); in glm_i128_interleave()
27 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
28 Reg1 = _mm_and_si128(Reg1, Mask4); in glm_i128_interleave()
32 Reg2 = _mm_slli_si128(Reg1, 1); in glm_i128_interleave()
33 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
34 Reg1 = _mm_and_si128(Reg1, Mask3); in glm_i128_interleave()
38 Reg2 = _mm_slli_epi32(Reg1, 4); in glm_i128_interleave()
39 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
650 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
669 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
95 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
98 GPRRegister::Encoded_Reg_##Reg1); \ in TEST_F()
101 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
107 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
120 GPRRegister::Encoded_Reg_##Reg1 < 4) { \ in TEST_F()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
97 __ mov(IceType_i##Size, Encoded_GPR_##Reg1(), Immediate(Value1)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
100 __ And(IceType_i32, Encoded_GPR_##Reg1(), Immediate(Mask##Size)); \ in TEST_F()
105 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
509 .addImm(Reg1) in InsertSEH()
519 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
520 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
527 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
557 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
560 .addImm(Reg1) in InsertSEH()
568 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
569 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
576 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 419 bool parseAddress(bool &HaveReg1, Register &Reg1,
835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
853 if (parseRegister(Reg1)) in parseAddress()
900 Register Reg1, Reg2; in parseAddress() local
904 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) in parseAddress()
911 if (parseAddressRegister(Reg1)) in parseAddress()
913 Base = Regs[Reg1.Num]; in parseAddress()
928 if (parseAddressRegister(Reg1)) in parseAddress()
933 Index = Regs[Reg1.Num]; in parseAddress()
935 Base = Regs[Reg1.Num]; in parseAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
137 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
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| D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 875 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
884 unsigned Temp = Reg1; in EmitInstrRegReg()
885 Reg1 = Reg2; in EmitInstrRegReg()
889 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
895 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
899 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
906 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
910 unsigned temp = Reg1; in EmitMovFPIntPair()
911 Reg1 = Reg2; in EmitMovFPIntPair()
914 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
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| D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
292 MIB3.addReg(Reg1); in adjustStackPtrBig()
296 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
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| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
387 if (Registers[i] == Reg1) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
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| D | MipsSEFrameLowering.cpp | 465 unsigned Reg1 = in emitPrologue() local
469 std::swap(Reg0, Reg1); in emitPrologue()
477 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
485 std::swap(Reg0, Reg1); in emitPrologue()
493 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
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| D | Mips16InstrInfo.h | 120 unsigned Reg1, unsigned Reg2) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
211 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
220 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
229 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
239 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
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| D | MipsMCCodeEmitter.cpp | 99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch() local
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
104 if (Reg0 < Reg1) in LowerCompactBranch()
107 if (Reg0 >= Reg1) in LowerCompactBranch()
111 if (Reg1 >= Reg0) in LowerCompactBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 187 unsigned Reg1,
402 unsigned Reg1, in getOperandGatherWeight() argument
415 if (Def->modifiesRegister(Reg1, TRI)) in getOperandGatherWeight()
540 unsigned Reg1 = OperandMasks[I].Reg; in collectCandidates() local
549 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) << in collectCandidates()
552 unsigned Weight = getOperandGatherWeight(MI, Reg1, Reg2, StallCycles); in collectCandidates()
557 unsigned FreeBanks1 = getFreeBanks(Reg1, SubReg1, Mask1, UsedBanks); in collectCandidates()
560 Candidates.push(Candidate(&MI, Reg1, FreeBanks1, Weight in collectCandidates()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
78 return contains(Reg1) && contains(Reg2); in contains()
740 uint16_t Reg1 = 0; variable
748 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
764 Reg0 = Reg1;
765 Reg1 = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 165 unsigned Reg1, bool isKill1, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
264 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in tryInlineAsm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 98 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
101 if (!Register::isPhysicalRegister(Reg1) || in contains()
104 return MC->contains(Reg1, Reg2); in contains()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 175 Register Reg1 = MI.getOperand(Idx1).getReg(); in commuteInstructionImpl() local
188 bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1) in commuteInstructionImpl()
196 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
204 Reg0 = Reg1; in commuteInstructionImpl()
221 CommutedMI->getOperand(Idx2).setReg(Reg1); in commuteInstructionImpl()
233 if (Register::isPhysicalRegister(Reg1)) in commuteInstructionImpl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1382 StringRef Reg1(R1); in processInstruction() local
1383 MO.setReg(matchRegister(Reg1)); in processInstruction()
1397 StringRef Reg1(R1); in processInstruction() local
1398 MO.setReg(matchRegister(Reg1)); in processInstruction()
1413 StringRef Reg1(R1); in processInstruction() local
1414 MO.setReg(matchRegister(Reg1)); in processInstruction()
1745 StringRef Reg1(R1); in processInstruction() local
1746 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1889 StringRef Reg1(R1); in processInstruction() local
1890 Rss.setReg(matchRegister(Reg1)); in processInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 1438 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1442 printRegName(O, Reg1); in printVectorListTwo()
1451 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1455 printRegName(O, Reg1); in printVectorListTwoSpaced()
1506 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1510 printRegName(O, Reg1); in printVectorListTwoAllLanes()
1553 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1557 printRegName(O, Reg1); in printVectorListTwoSpacedAllLanes()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 668 unsigned Reg1 = Reg; in lowerCRSpilling() local
673 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
713 unsigned Reg1 = Reg; in lowerCRRestore() local
719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
817 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
822 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 82 const DebugLoc &DL, unsigned Reg1,
449 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
455 .addReg(Reg1) in createRegSequence()
|