| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 31 const RegisterClassInfo &RegClassInfo, in AllocationOrder() argument
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
|
| D | BreakFalseDeps.cpp | 38 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
271 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
|
| D | RegAllocBase.cpp | 66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
|
| D | AllocationOrder.h | 45 const RegisterClassInfo &RegClassInfo,
|
| D | RegAllocBase.h | 69 RegisterClassInfo RegClassInfo; variable
|
| D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in __anon0e0c7b710111::PostRAScheduler
291 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
|
| D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; variable
|
| D | RegAllocGreedy.cpp | 810 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in canReassign()
922 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
923 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
1095 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
1128 unsigned MinCost = RegClassInfo.getMinCost(RC); in tryEvict()
1138 OrderLimit = RegClassInfo.getLastCostChange(RC); in tryEvict()
1153 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1690 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
2023 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
2090 if (!RegClassInfo.isProperSubClass(CurRC)) in tryInstructionSplit()
[all …]
|
| D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; variable
|
| D | RegAllocFast.cpp | 75 RegisterClassInfo RegClassInfo; member in __anona60479540111::RegAllocFast
716 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
763 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
1302 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
|
| D | CriticalAntiDepBreaker.cpp | 48 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
407 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
|
| D | MachineScheduler.cpp | 143 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
147 delete RegClassInfo; in ~MachineSchedContext()
387 RegClassInfo->runOnMachineFunction(*MF); in runOnMachineFunction()
1001 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1003 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1055 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1085 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1268 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
2760 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
|
| D | RegAllocBasic.cpp | 262 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
|
| D | AggressiveAntiDepBreaker.cpp | 130 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
|
| D | TargetRegisterInfo.cpp | 47 const RegClassInfo *const RCIs, in TargetRegisterInfo()
|
| D | MachinePipeliner.cpp | 221 RegClassInfo.runOnMachineFunction(*MF); in INITIALIZE_PASS_DEPENDENCY()
385 SwingSchedulerDAG SMS(*this, L, getAnalysis<LiveIntervals>(), RegClassInfo, in swingModuloScheduler()
1592 RecRPTracker.init(&MF, &RegClassInfo, &LIS, BB, BB->end(), false, true); in registerPressureFilter()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIPreAllocateWWMRegs.cpp | 44 RegisterClassInfo RegClassInfo; member in __anon8d02ff100111::SIPreAllocateWWMRegs
107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
177 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
|
| D | GCNSchedStrategy.cpp | 44 SGPRExcessLimit = Context->RegClassInfo in initialize()
46 VGPRExcessLimit = Context->RegClassInfo in initialize()
|
| D | SIMachineScheduler.h | 451 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 232 struct RegClassInfo { struct
244 const RegClassInfo *const RCInfos; argument
254 const RegClassInfo *const RCIs,
653 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
|
| D | MachineScheduler.h | 127 RegisterClassInfo *RegClassInfo; member
383 RegisterClassInfo *RegClassInfo;
427 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
|
| D | MachinePipeliner.h | 67 RegisterClassInfo RegClassInfo; variable
122 const RegisterClassInfo &RegClassInfo; variable
203 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) { in SwingSchedulerDAG()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.h | 99 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 109 RegisterClassInfo RegClassInfo; member
583 RegClassInfo.runOnMachineFunction(*MF); in findFreeReg()
587 for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) in findFreeReg()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 306 auto RegClassInfo = Names2RegClasses.find(Name); in getRegClass() local
307 if (RegClassInfo == Names2RegClasses.end()) in getRegClass()
309 return RegClassInfo->getValue(); in getRegClass()
|