| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.td | 101 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
107 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
122 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
135 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
144 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
157 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
163 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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| D | RISCVSubtarget.h | 52 RISCVRegisterInfo RegInfo; variable
76 return &RegInfo; in getRegisterInfo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 93 const MipsRegisterInfo &RegInfo; member in __anonaf7dbbba0111::ExpandPseudo
102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
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| D | MipsSERegisterInfo.cpp | 156 const MipsRegisterInfo *RegInfo = in eliminateFI() local
183 else if (RegInfo->needsStackRealignment(MF)) { in eliminateFI()
224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
225 Register Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
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| D | MipsSEISelLowering.cpp | 3037 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32() local
3068 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3074 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3106 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo() local
3137 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3143 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3173 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW() local
3184 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3191 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3219 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD() local
[all …]
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| D | Mips16ISelDAGToDAG.cpp | 72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| D | MipsMachineFunction.cpp | 68 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
77 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
78 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 117 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
135 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
138 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
152 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
167 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
168 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
181 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
193 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, in emitPrologue()
384 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
404 if (RegInfo->needsStackRealignment(MF)) { in emitPrologue()
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| D | ARMFrameLowering.cpp | 105 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
113 return (RegInfo->needsStackRealignment(MF) || in hasFP()
365 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); in emitPrologue() local
379 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
719 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { in emitPrologue()
751 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
753 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
758 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
774 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in emitEpilogue() local
783 Register FramePtr = RegInfo->getFrameRegister(MF); in emitEpilogue()
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| D | Thumb1InstrInfo.cpp | 58 const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); in copyPhysReg() local
59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
63 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 240 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
251 RegInfo->needsStackRealignment(MF)) in hasFP()
421 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in canUseAsPrologue() local
424 if (!RegInfo->needsStackRealignment(*MF)) in canUseAsPrologue()
453 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in shouldCombineCSRLocalStackBump() local
466 if (RegInfo->needsStackRealignment(MF)) in shouldCombineCSRLocalStackBump()
496 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in InsertSEH() local
505 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH()
506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH()
526 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 94 const SparcRegisterInfo &RegInfo = in emitPrologue() local
100 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); in emitPrologue()
158 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue()
171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
172 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue()
252 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
256 RegInfo->needsStackRealignment(MF) || in hasFP()
266 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local
284 } else if (RegInfo->needsStackRealignment(MF)) { in getFrameIndexReference()
298 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 113 const X86RegisterInfo &RegInfo,
242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local
244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction()
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
359 const X86RegisterInfo &RegInfo = in collectCallInfo() local
383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
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| D | X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
22 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
| D | ControlHeightReduction.cpp | 163 struct RegInfo { struct
164 RegInfo() : R(nullptr), HasBranch(false) {} in RegInfo() argument
165 RegInfo(Region *RegionIn) : R(RegionIn), HasBranch(false) {} in RegInfo() function
178 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { in CHRScope()
224 for (RegInfo &RI : Next->RegInfos) in append()
233 for (RegInfo &RI : RegInfos) in addSub()
250 [&Boundary](const RegInfo& RI) { in split()
255 SmallVector<RegInfo, 8> TailRegInfos; in split()
260 for (RegInfo &RI : TailRegInfos) in split()
271 [&Parent](const RegInfo& RI) { in split()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 105 const VRegInfo &RegInfo) const;
300 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local
301 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
306 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep()
459 const VRegInfo &RegInfo) const { in isUndefRegAtInput()
462 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
543 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce() local
544 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in runOnce()
551 if (isUndefRegAtInput(MO, RegInfo)) { in runOnce()
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| D | TargetRegisterInfo.cpp | 153 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
155 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { in printRegClassOrBank()
156 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
157 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
158 else if (RegInfo.getRegBankOrNull(Reg)) in printRegClassOrBank()
159 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); in printRegClassOrBank()
162 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
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| D | MIRPrinter.cpp | 122 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
264 const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
267 OS << printRegClassOrBank(Reg, RegInfo, TRI); in printRegClassOrBank()
287 const MachineRegisterInfo &RegInfo, in convert() argument
289 MF.TracksRegLiveness = RegInfo.tracksLiveness(); in convert()
292 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { in convert()
296 if (RegInfo.getVRegName(Reg) != "") in convert()
298 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); in convert()
299 unsigned PreferredReg = RegInfo.getSimpleHint(Reg); in convert()
306 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { in convert()
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| D | MachineInstr.cpp | 1141 const TargetRegisterInfo &RegInfo) { in substituteRegister() argument
1144 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1148 MO.substPhysReg(ToReg, RegInfo); in substituteRegister()
1154 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
1786 const TargetRegisterInfo *RegInfo, in addRegisterKilled() argument
1790 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); in addRegisterKilled()
1821 if (RegInfo->isSuperRegister(IncomingReg, Reg)) in addRegisterKilled()
1823 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterKilled()
1852 const TargetRegisterInfo *RegInfo) { in clearRegisterKills() argument
1854 RegInfo = nullptr; in clearRegisterKills()
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| D | PrologEpilogInserter.cpp | 388 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); in assignCalleeSavedSpillSlots() local
400 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) { in assignCalleeSavedSpillSlots()
419 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
422 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { in assignCalleeSavedSpillSlots()
434 unsigned Size = RegInfo->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
437 unsigned Align = RegInfo->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()
884 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
887 RegInfo->useFPForScavengingIndex(MF) && in calculateFrameObjectOffsets()
888 !RegInfo->needsStackRealignment(MF)); in calculateFrameObjectOffsets()
1073 (RegInfo->needsStackRealignment(MF) && MFI.getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 486 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in determineFrameLayout() local
488 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
494 !RegInfo->hasBasePointer(MF); // No special alignment. in determineFrameLayout()
563 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in replaceFPWithRealFP() local
564 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
565 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
659 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in findScratchRegister() local
660 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); in findScratchRegister()
705 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in twoUniqueScratchRegsRequired() local
707 bool HasBP = RegInfo->hasBasePointer(MF); in twoUniqueScratchRegsRequired()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VEFrameLowering.cpp | 181 const VERegisterInfo &RegInfo = in emitPrologue() local
187 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); in emitPrologue()
240 unsigned regFP = RegInfo.getDwarfRegNum(VE::SX9, true); in emitPrologue()
290 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
294 RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 313 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
319 [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>;
325 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
331 [RegInfo<2048,2048,2048>, RegInfo<4096,4096,4096>, RegInfo<2048,2048,2048>]>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.h | 26 const NVPTXRegisterInfo RegInfo; variable
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
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| D | NVPTXInstrInfo.cpp | 30 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {} in NVPTXInstrInfo()
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
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