| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 247 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
249 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
254 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 229 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
230 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
234 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 1070 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1072 if (RegVT == MVT::i8) { in LowerFormalArguments()
1074 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1081 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1098 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1103 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1199 EVT RegVT = VA.getLocVT(); in LowerCall() local
1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1215 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SwitchLoweringUtils.h | 208 MVT RegVT; member
222 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 485 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
486 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
489 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
495 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 643 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
644 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
649 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
656 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 788 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
790 RegVT = VA.getValVT(); in LowerFormalArguments()
792 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
794 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
800 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
801 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
802 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
803 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
807 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
809 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1302 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1303 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1308 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
1315 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 2679 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2680 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2718 MVT VT = BB.RegVT; in visitBitTestCase()
7970 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in GetRegistersForValue() local
7986 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in GetRegistersForValue()
7992 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in GetRegistersForValue()
7993 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
7997 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
8014 ValueVT = RegVT; in GetRegistersForValue()
8043 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in GetRegistersForValue()
[all …]
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| D | TargetLowering.cpp | 6609 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
6610 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
6707 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
6709 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
6713 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
6729 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), in expandUnalignedLoad()
6747 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
6857 MVT RegVT = getRegisterType( in expandUnalignedStore() local
6862 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
6866 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore()
[all …]
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| D | LegalizeIntegerTypes.cpp | 1190 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
1196 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1212 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3650 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3652 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3657 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3663 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3664 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3665 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3667 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3671 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 639 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
646 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
650 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
654 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
682 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
688 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
692 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS; in tryTLSXFormLoad()
696 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS; in tryTLSXFormLoad()
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| D | PPCISelLowering.cpp | 5301 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5305 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5311 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5313 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5318 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5320 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5353 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5374 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5377 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff); in buildCallOperands()
5384 RegVT)); in buildCallOperands()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3400 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3403 if (RegVT == MVT::i32) in LowerFormalArguments()
3405 else if (RegVT == MVT::i64) in LowerFormalArguments()
3407 else if (RegVT == MVT::f16) in LowerFormalArguments()
3409 else if (RegVT == MVT::f32) in LowerFormalArguments()
3411 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
3413 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
3415 else if (RegVT.isScalableVector() && in LowerFormalArguments()
3416 RegVT.getVectorElementType() == MVT::i1) in LowerFormalArguments()
3418 else if (RegVT.isScalableVector()) in LowerFormalArguments()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3400 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3412 if (RegVT == MVT::i8) in LowerFormalArguments()
3414 else if (RegVT == MVT::i16) in LowerFormalArguments()
3416 else if (RegVT == MVT::i32) in LowerFormalArguments()
3418 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
3420 else if (RegVT == MVT::f32) in LowerFormalArguments()
3422 else if (RegVT == MVT::f64) in LowerFormalArguments()
3424 else if (RegVT == MVT::f80) in LowerFormalArguments()
3426 else if (RegVT == MVT::f128) in LowerFormalArguments()
3428 else if (RegVT.is512BitVector()) in LowerFormalArguments()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2676 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
2690 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
4055 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4088 if (RegVT == MVT::f16) in LowerFormalArguments()
4090 else if (RegVT == MVT::f32) in LowerFormalArguments()
4092 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16) in LowerFormalArguments()
4094 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16) in LowerFormalArguments()
4096 else if (RegVT == MVT::i32) in LowerFormalArguments()
4104 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
4123 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
[all …]
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