| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
123 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
124 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
234 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
235 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
236 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
237 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
238 def ToAext64: OutPatFrag<(ops node:$Rs),
239 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
241 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
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| D | HexagonIntrinsics.td | 12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
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| D | HexagonPatternsHVX.td | 195 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
196 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
197 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
198 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
199 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
200 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
214 def Vsplatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
215 def Vsplatrh: OutPatFrag<(ops node:$Rs),
216 (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
217 def Vsplatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
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| D | HexagonConstExtenders.cpp | 293 Register Rs; member
298 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {} in ExtExpr()
301 return Rs.Reg == 0; in trivial()
304 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg; in operator ==()
310 if (Rs != Ex.Rs) in operator <()
311 return Rs < Ex.Rs; in operator <()
445 : Rs(R), HRI(I) {} in PrintRegister()
446 HCE::Register Rs; member
452 if (P.Rs.Reg != 0) in operator <<()
453 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
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| D | HexagonIntrinsicsV5.td | 41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
302 // Rd=[cround|round](Rs,Rt)[:sat]
303 // Rd=[cround|round](Rs,#u5)[:sat]
328 // Rdd=vmpyb[s]u(Rs,Rt)
332 // Rxx+=vmpyb[s]u(Rs,Rt)
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| D | HexagonSplitDouble.cpp | 103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second; in isInduction() local
148 if (Rs.find(Reg) != Rs.end()) in isInduction()
375 Register Rs = MI->getOperand(1).getReg(); in profit() local
377 return profit(Rs) + profit(Rt); in profit()
477 USet &Rs) { in collectIndRegsForLoop() argument
561 Rs.insert(DP.begin(), End); in collectIndRegsForLoop()
562 Rs.insert(CmpR1); in collectIndRegsForLoop()
563 Rs.insert(CmpR2); in collectIndRegsForLoop()
567 dump_partition(dbgs(), Rs, *TRI); in collectIndRegsForLoop()
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| D | HexagonPseudo.td | 42 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
51 let Inst{27} = Rs;
187 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
188 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
189 bits<5> Rs;
195 let Inst{20-16} = Rs;
264 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
314 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
333 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
426 (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>,
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| /third_party/mesa3d/src/gallium/frontends/clover/util/ |
| D | algorithm.hpp | 75 template<typename... Rs>
76 adaptor_range<zips, Rs...>
77 zip(Rs &&... rs) { in zip()
78 return map(zips(), std::forward<Rs>(rs)...); in zip()
101 template<typename F, typename... Rs>
103 for_each(F &&f, Rs &&... rs) { in for_each()
104 eval(map(std::forward<F>(f), std::forward<Rs>(rs)...)); in for_each()
172 template<typename F, typename... Rs>
174 all_of(F &&f, Rs &&... rs) { in all_of()
187 template<typename F, typename... Rs>
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| D | range.hpp | 244 template<typename G, typename... Rs>
245 adaptor_range(G &&f, Rs &&... os) : in adaptor_range()
246 f(std::forward<G>(f)), os(std::forward<Rs>(os)...) { in adaptor_range()
371 template<typename F, typename... Rs>
372 adaptor_range<F, Rs...>
373 map(F &&f, Rs &&... rs) { in map()
374 return { std::forward<F>(f), std::forward<Rs>(rs)... }; in map()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local
222 Rs = L.getOperand(1); in getCompoundInsn()
228 CompoundInsn->addOperand(Rs); in getCompoundInsn()
235 Rs = L.getOperand(1); in getCompoundInsn()
241 CompoundInsn->addOperand(Rs); in getCompoundInsn()
248 Rs = L.getOperand(1); in getCompoundInsn()
254 CompoundInsn->addOperand(Rs); in getCompoundInsn()
261 Rs = L.getOperand(1); in getCompoundInsn()
267 CompoundInsn->addOperand(Rs); in getCompoundInsn()
282 Rs = L.getOperand(1); in getCompoundInsn()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
639 Rs))); in DecodeDAHIDATIMMR6()
641 Rs))); in DecodeDAHIDATIMMR6()
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
653 Rs))); in DecodeDAHIDATI()
655 Rs))); in DecodeDAHIDATI()
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
680 if (Rs >= Rt) { in DecodeAddiGroupBranch()
683 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
691 Rs))); in DecodeAddiGroupBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
212 Opcode |= Rs << 21; in emitRsRt()
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
224 Opcode |= Rs << 21; in emitRtRsImm16()
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
248 Opcode |= Rs << 21; in emitRtRsImm16Rel()
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16() local
261 Opcode |= Rs << 21; in emitFtRsImm16()
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt() local
288 Opcode |= Rs << 21; in emitRdRsRt()
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| /third_party/flutter/skia/third_party/externals/icu/source/data/curr/ |
| D | root.txt | 147 LKR{"Rs"}
154 MUR{"Rs"}
161 NPR{"Rs"}
164 PKR{"Rs"}
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| D | sd.txt | 446 "Rs",
699 LKR{"Rs"}
704 MUR{"Rs"}
711 NPR{"Rs"}
714 PKR{"Rs"}
|
| /third_party/icu/icu4c/source/data/curr/ |
| D | root.txt | 153 LKR{"Rs"}
160 MUR{"Rs"}
167 NPR{"Rs"}
170 PKR{"Rs"}
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| D | mt.txt | 649 LKR{"Rs"}
654 MUR{"Rs"}
660 NPR{"Rs"}
663 PKR{"Rs"}
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| D | sd.txt | 447 "Rs",
700 LKR{"Rs"}
705 MUR{"Rs"}
712 NPR{"Rs"}
715 PKR{"Rs"}
|
| /third_party/skia/third_party/externals/icu/source/data/curr/ |
| D | root.txt | 153 LKR{"Rs"}
160 MUR{"Rs"}
167 NPR{"Rs"}
170 PKR{"Rs"}
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| D | mt.txt | 649 LKR{"Rs"}
654 MUR{"Rs"}
660 NPR{"Rs"}
663 PKR{"Rs"}
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| D | sd.txt | 447 "Rs",
700 LKR{"Rs"}
705 MUR{"Rs"}
712 NPR{"Rs"}
715 PKR{"Rs"}
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() argument
155 switch (Rs) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
184 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeI()
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
190 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeII()
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| /third_party/openGLES/extensions/NV/ |
| D | NV_blend_square.txt | 78 SRC_COLOR (Rs, Gs, Bs, As) NEW
79 ONE_MINUS_SRC_COLOR (1, 1, 1, 1) - (Rs, Gs, Bs, As) NEW
99 SRC_COLOR (Rs, Gs, Bs, As)
100 ONE_MINUS_SRC_COLOR (1, 1, 1, 1) - (Rs, Gs, Bs, As)
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| /third_party/skia/third_party/externals/opengl-registry/extensions/NV/ |
| D | NV_blend_square.txt | 78 SRC_COLOR (Rs, Gs, Bs, As) NEW
79 ONE_MINUS_SRC_COLOR (1, 1, 1, 1) - (Rs, Gs, Bs, As) NEW
99 SRC_COLOR (Rs, Gs, Bs, As)
100 ONE_MINUS_SRC_COLOR (1, 1, 1, 1) - (Rs, Gs, Bs, As)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1618 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1628 TmpInst.addOperand(Rs); in processInstruction()
1638 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1648 TmpInst.addOperand(Rs); in processInstruction()
1658 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1668 TmpInst.addOperand(Rs); in processInstruction()
1681 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1698 TmpInst.addOperand(Rs); in processInstruction()
1714 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1716 TmpInst.addOperand(Rs); in processInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
140 Register Reg = Rs == GAReg ? Rt : Rs; in matchLargeOffset()
|