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Searched refs:SI_SGPR_VS_STATE_BITS (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp1238 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state); in si_emit_vs_state()
1244 radeon_set_sh_reg(gs_base + SI_SGPR_VS_STATE_BITS * 4, gs_state); in si_emit_vs_state()
1248 radeon_set_sh_reg(gs_copy_base + SI_SGPR_VS_STATE_BITS * 4, gs_state); in si_emit_vs_state()
1250 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state); in si_emit_vs_state()
1251 radeon_set_sh_reg(tes_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state); in si_emit_vs_state()
1253 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state); in si_emit_vs_state()
Dsi_shader.h179 SI_SGPR_VS_STATE_BITS = SI_NUM_RESOURCE_SGPRS, enumerator
Dsi_shader_llvm_gs.c69 ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); in si_set_es_return_value_for_gs()
Dsi_shader_llvm_tess.c555 ret = si_insert_input_ret(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); in si_set_ls_return_value_for_tcs()
Dgfx10_shader_ngg.c1434 ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); in gfx10_ngg_culling_build_end()