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Searched refs:SI_SH_REG_END (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_cs.h100 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
118 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_idx()
134 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in gfx10_set_sh_reg_idx3()
/third_party/mesa3d/src/amd/common/
Dsid.h33 #define SI_SH_REG_END 0x0000C000 macro
42 #define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET)
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600d_common.h32 #define SI_SH_REG_END 0x0000C000 macro
Dr600_cs.h169 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h115 assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
122 assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
Dsi_pm4.c87 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) { in si_pm4_set_reg()