| /third_party/openssl/crypto/sha/asm/ |
| D | sha512-mips.pl | 103 $SRL="dsrl"; # shift right logical
118 $SRL="srl"; # shift right logical
216 $SRL $h,$e,@Sigma1[0]
220 $SRL $tmp0,$e,@Sigma1[1]
224 $SRL $tmp0,$e,@Sigma1[2]
231 $SRL $h,$a,@Sigma0[0]
236 $SRL $tmp0,$a,@Sigma0[1]
240 $SRL $tmp0,$a,@Sigma0[2]
267 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
273 $SRL $tmp3,@X[14],@sigma1[0]
[all …]
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| D | sha512-sparcv9.pl | 70 $SRL="srlx"; # shift right logical
96 $SRL="srl"; # shift right logical
234 $SRL $e,@Sigma1[0],$h !! $i
238 $SRL $e,@Sigma1[1],$tmp0
242 $SRL $e,@Sigma1[2],$tmp0
249 $SRL $a,@Sigma0[0],$h
254 $SRL $a,@Sigma0[1],$tmp0
258 $SRL $a,@Sigma0[2],$tmp0
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 36 SRL = 0x27, enumerator
94 case SRL: in lanaiAluCodeToString()
113 .Case("srl", SRL) in stringToLanaiAluCode()
136 case ISD::SRL: in isdToLanaiAluCode()
137 return AluCode::SRL; in isdToLanaiAluCode()
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| D | LanaiMemAluCombiner.cpp | 222 return LPAC::SRL; in mergedAluCode()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. in getArithmeticInstrCost()
471 { ISD::SRL, MVT::v4i32, 1 }, // psrld. in getArithmeticInstrCost()
472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. in getArithmeticInstrCost()
499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
[all …]
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| D | X86ISelDAGToDAG.cpp | 704 case ISD::SRL: in IsProfitableToFold()
857 case ISD::SRL: { in PreprocessISelDAG()
868 case ISD::SRL: NewOpc = X86ISD::VSRLV; break; in PreprocessISelDAG()
1635 if (Shift.getOpcode() != ISD::SRL || in foldMaskAndShiftToExtract()
1649 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract()
1771 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || in foldMaskAndShiftToScale()
1830 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); in foldMaskAndShiftToScale()
1859 if (Shift.getOpcode() != ISD::SRL || in foldMaskedShiftToBEXTR()
1885 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); in foldMaskedShiftToBEXTR()
2007 case ISD::SRL: { in matchAddressRecursively()
[all …]
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| /third_party/libffi/src/mips/ |
| D | n32.S | 137 SRL t4, t6, 1*FFI_FLAG_BITS
148 SRL t4, t6, 2*FFI_FLAG_BITS
159 SRL t4, t6, 3*FFI_FLAG_BITS
170 SRL t4, t6, 4*FFI_FLAG_BITS
181 SRL t4, t6, 5*FFI_FLAG_BITS
192 SRL t4, t6, 6*FFI_FLAG_BITS
203 SRL t4, t6, 7*FFI_FLAG_BITS
227 SRL t6, 8*FFI_FLAG_BITS
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| D | ffitarget.h | 152 # define SRL srl macro
159 # define SRL dsrl macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 90 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
355 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
407 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
419 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
700 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSAT()
776 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
999 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
1157 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
1292 case ISD::SRL: in PromoteIntegerOperand()
1897 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
[all …]
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| D | TargetLowering.cpp | 1337 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1347 Opc = ISD::SRL; in SimplifyDemandedBits()
1390 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
1417 case ISD::SRL: { in SimplifyDemandedBits()
1449 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1485 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
1522 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
1530 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
1805 case ISD::SRL: in SimplifyDemandedBits()
1808 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
[all …]
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| D | DAGCombiner.cpp | 1271 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1541 case ISD::SRL: return visitSRL(N); in visit()
1663 case ISD::SRL: in combine()
2054 if (!C || ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2073 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL; in foldAddSubOfSignBit()
2995 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
2998 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3249 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
3840 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
3949 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitUDIVLike()
[all …]
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| D | LegalizeVectorOps.cpp | 387 case ISD::SRL: in LegalizeOp()
788 SDValue Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
1222 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
1239 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBITREVERSE()
1340 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) { in ExpandUINT_TO_FLOAT()
1367 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord); in ExpandUINT_TO_FLOAT()
|
| D | LegalizeDAG.cpp | 584 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
596 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
1178 case ISD::SRL: in LegalizeOp()
1549 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
2625 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT)); in ExpandBITREVERSE()
2632 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT)); in ExpandBITREVERSE()
2639 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT)); in ExpandBITREVERSE()
2652 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT)); in ExpandBITREVERSE()
2676 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in ExpandBSWAP()
2677 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in ExpandBSWAP()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
|
| /third_party/openssl/crypto/bn/asm/ |
| D | mips.pl | 69 $SRL="dsrl";
84 $SRL="srl";
930 $SRL $at,$a1,$t1
945 $SRL $DH,$a2,4*$BNSZ # bits
954 $SRL $HH,$a0,4*$BNSZ # bits
955 $SRL $QT,4*$BNSZ # q=0xffffffff
962 $SRL $at,$a1,4*$BNSZ # bits
987 $SRL $HH,$a0,4*$BNSZ # bits
988 $SRL $QT,4*$BNSZ # q=0xffffffff
995 $SRL $at,$a1,4*$BNSZ # bits
[all …]
|
| /third_party/libphonenumber/resources/carrier/en/ |
| D | 995.txt | 37 9955520|Premium Net International SRL
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 67 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
129 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_32.c | 138 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); in emit_single_op()
203 return push_inst(compiler, SRL | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_FLAG); in emit_single_op()
336 return push_inst(compiler, SRL | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_FLAG); in emit_single_op()
406 EMIT_SHIFT(SRL, SRLV); in emit_single_op()
|
| D | sljitNativeMIPS_64.c | 251 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_… in emit_single_op()
316 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), … in emit_single_op()
449 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), … in emit_single_op()
524 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 811 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
812 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
852 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
853 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
856 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1106 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1270 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1420 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1477 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1522 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
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| D | AMDGPUISelLowering.cpp | 372 setOperationAction(ISD::SRL, VT, Expand); in AMDGPUTargetLowering()
489 setTargetDAGCombine(ISD::SRL); in AMDGPUTargetLowering()
1823 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
2452 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64, in LowerINT_TO_FP32()
2632 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
2636 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2645 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2677 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
2685 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
2700 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 805 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
945 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
2352 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
2353 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
2402 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2403 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2446 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2477 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
2584 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, in lowerShiftLeftParts()
2586 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); in lowerShiftLeftParts()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelDAGToDAG.cpp | 136 case ISD::SRL: { in Select()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 78 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
81 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
343 case ISD::SRL: in LowerOperation()
986 case ISD::SRL: in LowerShifts()
998 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
|