| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 560 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
563 if (!isRegUsed(SReg)) { in scavengeRegister()
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); in scavengeRegister()
565 return SReg; in scavengeRegister()
571 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); in scavengeRegister()
575 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
577 return SReg; in scavengeRegister()
668 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
670 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
672 return SReg; in scavengeVReg()
[all …]
|
| D | LivePhysRegs.cpp | 263 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { in addLiveIns() local
264 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) { in addLiveIns()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
154 if (!Register::isVirtualRegister(SReg)) in getPrefSPRLane()
155 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
165 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
[all …]
|
| D | ARMBaseInstrInfo.cpp | 4867 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
4868 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4875 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 382 unsigned SReg = AMDGPU::NoRegister; in optimizeVccBranch() local
384 SReg = Op2.getReg(); in optimizeVccBranch()
388 if (M->definesRegister(SReg, TRI)) in optimizeVccBranch()
390 if (M->modifiesRegister(SReg, TRI)) in optimizeVccBranch()
392 ReadsSreg |= M->readsRegister(SReg, TRI); in optimizeVccBranch()
412 if (SReg == ExecReg) { in optimizeVccBranch()
|
| D | SIShrinkInstructions.cpp | 746 Register SReg = Src2->getReg(); in runOnMachineFunction() local
747 if (Register::isVirtualRegister(SReg)) { in runOnMachineFunction()
748 MRI.setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
751 if (SReg != VCCReg) in runOnMachineFunction()
|
| D | SIInstrInfo.cpp | 834 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
835 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
842 .addReg(SReg); in insertVectorSelect()
847 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
849 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
857 .addReg(SReg); in insertVectorSelect()
861 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
863 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
871 .addReg(SReg); in insertVectorSelect()
877 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
[all …]
|
| D | SIRegisterInfo.td | 806 defm SSrc : RegImmOperand<"SReg", "SSrc">;
818 defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
|
| D | SIInstructions.td | 967 // FIXME: Why do only some of these type combinations for SReg and
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 135 void setIsSplitFromReg(Register virtReg, unsigned SReg) { in setIsSplitFromReg() argument
136 Virt2SplitMap[virtReg.id()] = SReg; in setIsSplitFromReg()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 1126 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
1130 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1135 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1161 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
|
| D | PPCISelLowering.cpp | 10880 Register SReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
10881 BuildMI(BB, dl, TII->get(PPC::AND), SReg) in EmitPartwordAtomicBinary()
10884 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary()
10889 .addReg(SReg) in EmitPartwordAtomicBinary()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4751 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4759 if (DReg == SReg) { in expandRotation()
4767 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4772 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4798 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4799 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4814 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4826 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4831 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4840 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 205 IValueT SReg = EncodedQReg << 2; in mapQRegToSReg() local
206 assert(SReg < RegARM32::getNumSRegs()); in mapQRegToSReg()
207 return SReg; in mapQRegToSReg()
|