| /third_party/ffmpeg/libavcodec/arm/ |
| D | mlpdsp_armv5te.S | 38 ST0 .req v5 label
192 SHIFT .req ST0
225 mov SHIFT, ST0
236 ldr ST0, [PSAMP]
239 and ST0, ST0, MASK
241 str ST0, [PST, #-4]!
242 str ST0, [PST, #4 * (MAX_BLOCKSIZE + MAX_FIR_ORDER)]
243 str ST0, [PSAMP], #4 * MAX_CHANNELS
408 ldm v1, {ST0,ST1,I,PSAMP}
411 movs ST2, ST0, lsl #29 // shift is in range 0-15; we want to special-case 0 and 8
[all …]
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| /third_party/libunwind/src/x86/ |
| D | init.h | 44 c->dwarf.loc[ST0] = DWARF_REG_LOC (&c->dwarf, UNW_X86_ST0); in common_init()
45 for (i = ST0 + 1; i < DWARF_NUM_PRESERVED_REGS; ++i) in common_init()
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| D | unwind_i.h | 47 #define ST0 11 macro
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| D | Gget_save_loc.c | 50 case UNW_X86_ST0: loc = c->dwarf.loc[ST0]; break; in unw_get_save_loc()
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| D | Gregs.c | 130 loc = c->dwarf.loc[ST0]; in tdep_access_fpreg()
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| D | Gos-freebsd.c | 141 c->dwarf.loc[ST0] = DWARF_NULL_LOC; in x86_handle_signal_frame()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
852 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1111 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true)); in handleZeroArgFP()
1157 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true)); in handleOneArgFP()
1647 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
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| D | X86Instr3DNow.td | 78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
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| D | X86RegisterInfo.cpp | 573 Reserved.set(X86::ST0 + n); in getReservedRegs()
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| D | X86RegisterInfo.td | 191 // MMX Registers. These are actually aliased to ST0 .. ST7
282 def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>;
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| D | X86InstrControl.td | 19 // The X86retflag return instructions are variadic because we may add ST0 and
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| D | X86InstrFPStack.td | 677 let Uses = [ST0, FPCW] in {
686 let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in {
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| D | X86InstrMMX.td | 156 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
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| D | X86InstrCompiler.td | 475 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
495 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
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| D | X86InstrInfo.td | 3346 (Inst ST0), EmitAlias>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86IntelInstPrinter.cpp | 441 if (Reg == X86::ST0) in printSTiRegOperand()
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| D | X86ATTInstPrinter.cpp | 484 if (Reg == X86::ST0) in printSTiRegOperand()
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| D | X86MCTargetDesc.cpp | 116 {codeview::RegisterId::ST0, X86::FP0}, in initLLVMToSEHAndCVRegMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 155 ST0 = 135,
1271 { X86::ST0 },
2396 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2748 { 33U, X86::ST0 },
2801 { 12U, X86::ST0 },
2846 { 11U, X86::ST0 },
2915 { 33U, X86::ST0 },
2968 { 12U, X86::ST0 },
3013 { 11U, X86::ST0 },
3091 { X86::ST0, 33U },
[all …]
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| D | X86GenAsmMatcher.inc | 5046 Inst.addOperand(MCOperand::createReg(X86::ST0));
5301 MCK_ST0, // register class 'ST0'
7308 case X86::ST0: OpKind = MCK_ST0; break;
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| D | X86GenInstrInfo.inc | 16600 static const MCPhysReg ImplicitList31[] = { X86::ST0, X86::FPCW, 0 };
16608 …X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::ST0, X86::ST1, X86::ST2…
16673 …X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2…
16674 …X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2…
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 123 CV_REGISTER(ST0, 128)
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| /third_party/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 210 #define ST0 %st(0) macro
212 #define ST0 %st macro
891 #define ST0 st0 macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 2206 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); in translateFPRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1184 if (RegNo == X86::ST0) { in ParseRegister()
1197 case 0: RegNo = X86::ST0; break; in ParseRegister()
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