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Searched refs:SubRC (Results 1 – 7 of 7) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
47 if (!RC.hasSubClassEq(&SubRC)) in verify()
52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
54 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp179 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
180 if (SubRC->isAllocatable()) in getAllocatableClass()
181 return SubRC; in getAllocatableClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.h81 const TargetRegisterClass &SubRC,
DSIInstrInfo.h74 const TargetRegisterClass *SubRC) const;
80 const TargetRegisterClass *SubRC) const;
DAMDGPUInstructionSelector.cpp205 const TargetRegisterClass &SubRC, in getSubOperand64() argument
210 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
DSIInstrInfo.cpp3866 const TargetRegisterClass *SubRC) in buildExtractSubReg()
3870 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
3899 const TargetRegisterClass *SubRC) const { in buildExtractSubRegOrImm()
3910 SubIdx, SubRC); in buildExtractSubRegOrImm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp4457 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
4461 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
4467 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
4472 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()