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Searched refs:TYPE_U64 (Results 1 – 19 of 19) sorted by relevance

/third_party/mesa3d/src/nouveau/codegen/
Dnv50_ir_inlines.h69 case TYPE_U64: in typeSizeof()
93 case TYPE_U64: in typeSizeofLog2()
112 case 8: return flt ? TYPE_F64 : (sgn ? TYPE_S64 : TYPE_U64);
139 case TYPE_U64: in isSignedType()
151 case TYPE_U64: return TYPE_S64; in intTypeToSigned()
Dnv50_ir_lowering_helper.cpp62 if (!(dTy == TYPE_U64 || dTy == TYPE_S64)) in handleABS()
94 (dTy == TYPE_U32 && sTy == TYPE_U64)) { in handleCVT()
104 } else if (dTy == TYPE_U64 && sTy == TYPE_U32) { in handleCVT()
116 if (!(dTy == TYPE_U64 || dTy == TYPE_S64)) in handleMAXMIN()
Dnv50_ir_emit_gv100.cpp826 case TYPE_U64: emitField(73, 2, 1); break; in emitSHF()
881 case TYPE_U64 : dType = 2; break; in emitATOM()
896 case TYPE_U64: dType = 2; break; in emitATOM()
928 case TYPE_U64: dType = 2; break; in emitATOMS()
948 case TYPE_U64: dType = 2; break; in emitATOMS()
1151 case TYPE_U64: dType = 2; break; in emitRED()
1479 case TYPE_U64: type = 2; break; in emitSUATOM()
1525 case TYPE_U64: type = 5; break; in emitSULD()
Dnv50_ir_from_tgsi.cpp617 return nv50_ir::TYPE_U64; in inferSrcType()
679 return nv50_ir::TYPE_U64; in inferDstType()
3926 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1); in handleInstruction()
3971 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
3985 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
3997 mkOp2(OP_MERGE, TYPE_U64, src0, srcComp[0], srcComp[1]); in handleInstruction()
4020 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4032 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4057 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4060 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]); in handleInstruction()
[all …]
Dnv50_ir_lowering_gv100.cpp80 src2 = bld.mkOp2(OP_MERGE, TYPE_U64, bld.getSSA(8), src2s[0], src2s[1])->getDef(0); in handleIMAD_HIGH()
85 bld.mkOp3(OP_MAD, isSignedType(i->sType) ? TYPE_S64 : TYPE_U64, def, in handleIMAD_HIGH()
341 bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), dest[0], dest[1]); in handleDMNMX()
Dnv50_ir_build_util.cpp392 imm->reg.type = TYPE_U64; in mkImm()
442 return mkOp1v(OP_MOV, TYPE_U64, dst ? dst : getScratch(8), mkImm(u)); in loadImm()
598 case TYPE_U64: hTy = TYPE_U32; break; in split64BitOpPostRA()
Dnv50_ir_lowering_nvc0.cpp108 bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), def[0], def[1]); in handleRCPRSQLib()
150 bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]); in handleRCPRSQ()
263 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]); in handleShift()
292 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]); in handleShift()
1669 base = bld.mkOp2v(OP_ADD, TYPE_U64, base, base, ptr); in handleATOM()
1779 mkLoadv(TYPE_U64, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U64, off), ptr); in loadResInfo64()
1792 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U64, off + 8), ptr); in loadResLength32()
2160 bld.mkOp2(OP_MERGE, TYPE_U64, addr, bf, eau); in processSurfaceCoordsNVE4()
2163 bld.mkOp2(OP_ADD, TYPE_U64, addr, addr, off); in processSurfaceCoordsNVE4()
2573 su->dType = TYPE_U64; in handleSurfaceOpNVC0()
[all …]
Dnv50_ir_emit_gm107.cpp2244 case TYPE_U64: in emitSHF()
2649 case TYPE_U64: dType = 1; break; in emitATOM()
2659 case TYPE_U64: dType = 2; break; in emitATOM()
2689 case TYPE_U64: dType = 1; break; in emitATOMS()
2700 case TYPE_U64: dType = 2; break; in emitATOMS()
2728 case TYPE_U64: dType = 2; break; in emitRED()
3338 case TYPE_U64: type = 5; break; in emitSULDx()
3370 case TYPE_U64: type = 2; break; in emitSUREDx()
Dnv50_ir.cpp394 case TYPE_U64: in isInteger()
423 if (reg.type == TYPE_U64 || reg.type == TYPE_S64) in isPow2()
446 case TYPE_U64: in applyLog2()
Dnv50_ir_emit_nv50.cpp589 case TYPE_U64: enc = 0x4; break; in emitLoadStoreSizeLG()
1378 case TYPE_U64: code[1] = 0x44404000; break; in emitCVT()
1396 case TYPE_U64: in emitCVT()
1409 case TYPE_U64: code[1] = 0x40404000; break; in emitCVT()
Dnv50_ir_print.cpp529 case TYPE_U64: in print()
Dnv50_ir.h321 TYPE_U64, // 64 bit operations are only lowered after register allocation enumerator
Dnv50_ir_emit_gk110.cpp2130 case TYPE_U64: in emitLoadStoreType()
2412 case TYPE_U64: code[1] |= 0x00200000; break; in emitATOM()
Dnv50_ir_from_nir.cpp1233 (indirect0 || !prog->getTarget()->isAccessSupported(file, TYPE_U64))) { in loadFrom()
2727 } else if (dType == TYPE_S64 || dType == TYPE_U64) { in visit()
2851 mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp); in visit()
Dnv50_ir_emit_nvc0.cpp1820 case TYPE_U64: in emitLoadStoreType()
2105 if (i->dType == TYPE_U64) { in emitATOM()
Dnv50_ir_lowering_nv50.cpp71 case TYPE_S64: fTy = TYPE_U64; break; in expandIntegerMUL()
78 case TYPE_U64: hTy = TYPE_U32; break; in expandIntegerMUL()
Dnv50_ir_peephole.cpp728 case TYPE_U64: in expr()
2586 case TYPE_U64: hTy = TYPE_U32; break; in visit()
/third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/spirv_assembly/
DvktSpvAsmTypeTests.cpp165 TYPE_U64, enumerator
529 return (isSigned) ? TYPE_I64 : TYPE_U64; in getInputType()
2883 …testCtx, "u64", "uint64 tests", "shaderInt64", "Int64", "OpTypeInt 64 0", TYPE_U64, 64, vectorSize) in SpvAsmTypeUint64Tests()
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/spirv_assembly/
DvktSpvAsmTypeTests.cpp165 TYPE_U64, enumerator
529 return (isSigned) ? TYPE_I64 : TYPE_U64; in getInputType()
2883 …testCtx, "u64", "uint64 tests", "shaderInt64", "Int64", "OpTypeInt 64 0", TYPE_U64, 64, vectorSize) in SpvAsmTypeUint64Tests()