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Searched refs:UsedRegs (Results 1 – 11 of 11) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallFrameOptimization.cpp114 DenseSet<unsigned int> &UsedRegs);
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
344 for (unsigned int U : UsedRegs) in classifyInstruction()
409 DenseSet<unsigned int> UsedRegs; in collectCallInfo() local
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
458 UsedRegs.insert(Reg); in collectCallInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb1FrameLowering.cpp582 const LivePhysRegs &UsedRegs, unsigned &PopReg, in findTemporariesForLR() argument
586 if (!UsedRegs.contains(Reg)) { in findTemporariesForLR()
653 LivePhysRegs UsedRegs(TRI); in emitPopSpecialFixUp() local
654 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
661 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
670 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
694 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
704 UsedRegs.stepBackward(*PrevMBBI); in emitPopSpecialFixUp()
705 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
DARMFastISel.cpp230 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2034 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, in FinishCall() argument
2061 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2062 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2080 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2284 SmallVector<Register, 4> UsedRegs; in ARMEmitLibcall() local
2285 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2288 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2428 SmallVector<Register, 4> UsedRegs; in SelectCall() local
2429 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
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DARMLoadStoreOptimizer.cpp863 DenseSet<unsigned> UsedRegs; in MergeOpsUpdate() local
872 UsedRegs.insert(Reg); in MergeOpsUpdate()
964 if (UsedRegs.count(MO.getReg())) in MergeOpsUpdate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/
DDispatchStage.cpp39 ArrayRef<unsigned> UsedRegs, in notifyInstructionDispatched() argument
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps)); in notifyInstructionDispatched()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp930 SmallVector<Register, 8> UsedRegs; in EmitMachineNode() local
939 UsedRegs.push_back(Reg); in EmitMachineNode()
948 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
956 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
964 UsedRegs.push_back(Reg); in EmitMachineNode()
970 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef()) in EmitMachineNode()
971 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DCallingConvLower.cpp37 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
64 UsedRegs[*AI/32] |= 1 << (*AI&31); in MarkAllocated()
DMachineBasicBlock.cpp921 SmallVector<unsigned, 4> UsedRegs; in SplitCriticalEdge() local
933 if (!is_contained(UsedRegs, Reg)) in SplitCriticalEdge()
934 UsedRegs.push_back(Reg); in SplitCriticalEdge()
1068 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); in SplitCriticalEdge()
DMachineInstr.cpp1951 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, in setPhysRegsDeadExcept() argument
1964 if (llvm::none_of(UsedRegs, in setPhysRegsDeadExcept()
1972 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); in setPhysRegsDeadExcept()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DCallingConvLower.h203 SmallVector<uint32_t, 16> UsedRegs; variable
286 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
DMachineInstr.h1434 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,