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Searched refs:VCSUNIT0 (Results 1 – 4 of 4) sorted by relevance

/third_party/mesa3d/src/intel/tools/
Daub_read.c211 case VCSUNIT0(EXECLIST_SUBMITPORT): /* video elsp */ in handle_memtrace_reg_write()
237 case VCSUNIT0(EXECLIST_SQ_CONTENTS): /* video elsq0 lo */ in handle_memtrace_reg_write()
240 case VCSUNIT0(EXECLIST_SQ_CONTENTS) + 4: /* video elsq0 hi */ in handle_memtrace_reg_write()
254 case VCSUNIT0(EXECLIST_CONTROL): /* video_elsc */ in handle_memtrace_reg_write()
Daub_write.c371 .elsp_reg = VCSUNIT0(EXECLIST_SUBMITPORT),
372 .elsq_reg = VCSUNIT0(EXECLIST_SQ_CONTENTS),
373 .status_reg = VCSUNIT0(EXECLIST_STATUS),
374 .control_reg = VCSUNIT0(EXECLIST_CONTROL),
509 case I915_ENGINE_CLASS_VIDEO: reg = VCSUNIT0(HWS_PGA); break; in write_hwsp()
575 register_write_out(aub, VCSUNIT0(GFX_MODE), 0x80008000 /* execlist enable */); in write_execlists_default_setup()
Dintel_context.h66 #define VCSUNIT0(reg) (VCSUNIT0_START + reg) macro
/third_party/mesa3d/docs/relnotes/
D22.2.0.rst3779 - intel/tools: add macros for gfx12+ variant of VCSUNIT0