Searched refs:VINTRP (Results 1 – 13 of 13) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrFormats.td | 33 field bit VINTRP = 0; 146 let TSFlags{13} = VINTRP; 344 let VINTRP = 1; 345 // VINTRP instructions read parameter values from LDS, but these parameter
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D | SIDefines.h | 40 VINTRP = 1 << 13, enumerator
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D | SIInstrInfo.h | 575 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP; in isVINTRP() 579 return get(Opcode).TSFlags & SIInstrFlags::VINTRP; in isVINTRP()
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D | SIInstructions.td | 31 // VINTRP Instructions 39 // FIXME: Specify SchedRW for VINTRP insturctions.
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/third_party/mesa3d/src/amd/compiler/ |
D | aco_opcodes.py | 76 VINTRP = 1 << 12 variable in Format 149 elif self == Format.VINTRP: 981 VINTRP = { variable 987 for (code, name) in VINTRP: 988 opcode(name, code, code, code, Format.VINTRP, InstrClass.Valu32)
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D | aco_opt_value_numbering.cpp | 101 case Format::VINTRP: return hash_murmur_32<Interp_instruction>(instr); in operator ()() 219 case Format::VINTRP: { in operator ()()
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D | README-ISA.md | 93 ## VINTRP encoding 199 ### VINTRP followed by a read with `v_readfirstlane` or `v_readlane`
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D | aco_validate.cpp | 127 else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) { in validate_ir() 137 base_format = Format::VINTRP; in validate_ir() 146 base_format == Format::VOPC || base_format == Format::VINTRP, in validate_ir()
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D | aco_ir.h | 103 VINTRP = 1 << 12, enumerator 1302 constexpr bool isVINTRP() const noexcept { return (uint16_t)format & (uint16_t)Format::VINTRP; } in isVINTRP()
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D | aco_print_ir.cpp | 350 case Format::VINTRP: { in print_instr_format_specific()
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D | aco_assembler.cpp | 300 case Format::VINTRP: { in emit_instruction()
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/third_party/mesa3d/docs/relnotes/ |
D | 20.2.0.rst | 4309 - aco: validate v_interp_*_f16 as VOP3 instructions instead of VINTRP 4310 - aco: emit v_interp_*_f16 instructions as VOP3 instead of VINTRP
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D | 19.3.0.rst | 3283 - aco: Support GFX10 VINTRP in aco_assembler.
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