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/third_party/flutter/skia/third_party/externals/libjpeg-turbo/simd/x86_64/
Djcphuff-sse2.asm38 pinsrw X0, word [BLOCK + T0 * 2], 0
43 pinsrw X0, word [BLOCK + T0 * 2], 1
48 pinsrw X0, word [BLOCK + T0 * 2], 2
53 pinsrw X0, word [BLOCK + T0 * 2], 3
58 pinsrw X0, word [BLOCK + T0 * 2], 4
63 pinsrw X0, word [BLOCK + T0 * 2], 5
68 pinsrw X0, word [BLOCK + T0 * 2], 6
73 pinsrw X0, word [BLOCK + T0 * 2], 7
84 pinsrw X0, word [BLOCK + T0 * 2], 0
88 pinsrw X0, word [BLOCK + T0 * 2], 1
[all …]
/third_party/libjpeg-turbo/simd/x86_64/
Djcphuff-sse2.asm36 pinsrw X0, word [BLOCK + T0 * 2], 0
41 pinsrw X0, word [BLOCK + T0 * 2], 1
46 pinsrw X0, word [BLOCK + T0 * 2], 2
51 pinsrw X0, word [BLOCK + T0 * 2], 3
56 pinsrw X0, word [BLOCK + T0 * 2], 4
61 pinsrw X0, word [BLOCK + T0 * 2], 5
66 pinsrw X0, word [BLOCK + T0 * 2], 6
71 pinsrw X0, word [BLOCK + T0 * 2], 7
82 pinsrw X0, word [BLOCK + T0 * 2], 0
86 pinsrw X0, word [BLOCK + T0 * 2], 1
[all …]
/third_party/skia/third_party/externals/libjpeg-turbo/simd/x86_64/
Djcphuff-sse2.asm36 pinsrw X0, word [BLOCK + T0 * 2], 0
41 pinsrw X0, word [BLOCK + T0 * 2], 1
46 pinsrw X0, word [BLOCK + T0 * 2], 2
51 pinsrw X0, word [BLOCK + T0 * 2], 3
56 pinsrw X0, word [BLOCK + T0 * 2], 4
61 pinsrw X0, word [BLOCK + T0 * 2], 5
66 pinsrw X0, word [BLOCK + T0 * 2], 6
71 pinsrw X0, word [BLOCK + T0 * 2], 7
82 pinsrw X0, word [BLOCK + T0 * 2], 0
86 pinsrw X0, word [BLOCK + T0 * 2], 1
[all …]
/third_party/libjpeg-turbo/simd/i386/
Djcphuff-sse2.asm35 pinsrw X0, word [BLOCK + T0 * 2], 0
40 pinsrw X0, word [BLOCK + T0 * 2], 1
45 pinsrw X0, word [BLOCK + T0 * 2], 2
50 pinsrw X0, word [BLOCK + T0 * 2], 3
55 pinsrw X0, word [BLOCK + T0 * 2], 4
60 pinsrw X0, word [BLOCK + T0 * 2], 5
65 pinsrw X0, word [BLOCK + T0 * 2], 6
70 pinsrw X0, word [BLOCK + T0 * 2], 7
81 pinsrw X0, word [BLOCK + T0 * 2], 0
85 pinsrw X0, word [BLOCK + T0 * 2], 1
[all …]
/third_party/flutter/skia/third_party/externals/libjpeg-turbo/simd/i386/
Djcphuff-sse2.asm37 pinsrw X0, word [BLOCK + T0 * 2], 0
42 pinsrw X0, word [BLOCK + T0 * 2], 1
47 pinsrw X0, word [BLOCK + T0 * 2], 2
52 pinsrw X0, word [BLOCK + T0 * 2], 3
57 pinsrw X0, word [BLOCK + T0 * 2], 4
62 pinsrw X0, word [BLOCK + T0 * 2], 5
67 pinsrw X0, word [BLOCK + T0 * 2], 6
72 pinsrw X0, word [BLOCK + T0 * 2], 7
83 pinsrw X0, word [BLOCK + T0 * 2], 0
87 pinsrw X0, word [BLOCK + T0 * 2], 1
[all …]
/third_party/skia/third_party/externals/libjpeg-turbo/simd/i386/
Djcphuff-sse2.asm35 pinsrw X0, word [BLOCK + T0 * 2], 0
40 pinsrw X0, word [BLOCK + T0 * 2], 1
45 pinsrw X0, word [BLOCK + T0 * 2], 2
50 pinsrw X0, word [BLOCK + T0 * 2], 3
55 pinsrw X0, word [BLOCK + T0 * 2], 4
60 pinsrw X0, word [BLOCK + T0 * 2], 5
65 pinsrw X0, word [BLOCK + T0 * 2], 6
70 pinsrw X0, word [BLOCK + T0 * 2], 7
81 pinsrw X0, word [BLOCK + T0 * 2], 0
85 pinsrw X0, word [BLOCK + T0 * 2], 1
[all …]
/third_party/openssl/crypto/sha/asm/
Dsha256-c64xplus.pl42 ($Xn,$X0,$K)=("B7","B8","B9");
117 || SWAP4 $Xn,$X0
121 || SWAP2 $X0,$X0
138 ADD $X0,$T1,$T1 ; T1 += X[i];
139 || STW $X0,*$Xib++
150 || MV $X0,$X14
151 || SWAP4 $Xn,$X0
152 SWAP2 $X0,$X0
177 ADD $X0,$T1,$T1 ; T1 += X[i];
178 || STW $X0,*$Xib++
[all …]
Dsha1-c64xplus.pl40 ($X0,$X2,$X8,$X13) = ("A26","B26","A27","B27");
137 || LDW *${XPA}++,$X0 ; fetches from X ring buffer are
162 || XOR $X0,$X2,$TX0 ; Xupdate XORs are 1 iteration ahead
163 || LDW *${XPA}++,$X0
193 || XOR $X0,$X2,$TX0
194 || LDW *${XPA}++,$X0
230 || XOR $X0,$X2,$TX0
231 || LDW *${XPA}++,$X0
270 || XOR $X0,$X2,$TX0
271 || LDW *${XPA}++,$X0
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td563 def : InstAlias<"nop", (ADDI X0, X0, 0)>;
592 def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
595 def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>;
600 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;
601 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
602 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
610 (BEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
612 (BNE GPR:$rs, X0, simm13_lsb0:$offset)>;
614 (BGE X0, GPR:$rs, simm13_lsb0:$offset)>;
616 (BGE GPR:$rs, X0, simm13_lsb0:$offset)>;
[all …]
DRISCVRegisterInfo.cpp29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
79 markSuperRegs(Reserved, RISCV::X0); // zero in getReservedRegs()
99 return PhysReg == RISCV::X0; in isConstantPhysReg()
DRISCVInstrInfoA.td172 (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
174 (AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
176 (AMOADD_W_RL GPR:$addr, (SUB X0, GPR:$incr))>;
178 (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
180 (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
339 (AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
341 (AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
343 (AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
345 (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
347 (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
DRISCVInstrInfoF.td250 def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>;
252 def : InstAlias<"fscsr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 2>;
256 def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 0>;
258 def : InstAlias<"fssr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 0>;
260 def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, FRM.Encoding, X0), 2>;
262 def : InstAlias<"fsrm $rs", (CSRRW X0, FRM.Encoding, GPR:$rs), 2>;
264 def : InstAlias<"fsrmi $imm", (CSRRWI X0, FRM.Encoding, uimm5:$imm), 2>;
266 def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, FFLAGS.Encoding, X0), 2>;
268 def : InstAlias<"fsflags $rs", (CSRRW X0, FFLAGS.Encoding, GPR:$rs), 2>;
270 def : InstAlias<"fsflagsi $imm", (CSRRWI X0, FFLAGS.Encoding, uimm5:$imm), 2>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td41 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.
42 // However, on windows, in some circumstances, the SRet is passed in X0 or X1
44 // passed in the alternative register (X0 or X1), not X8:
45 // - X0 for non-instance methods.
56 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1], [W0, W1]>>>>>,
93 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
95 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
96 [X0, X1, X3, X5]>>>,
101 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
142 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
[all …]
DAArch64CleanupLocalDynamicTLSPass.cpp105 TII->get(TargetOpcode::COPY), AArch64::X0) in replaceTLSBaseAddrCall()
128 .addReg(AArch64::X0); in setRegister()
DAArch64AsmPrinter.cpp322 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
473 .addReg(AArch64::X0) in EmitHwasanMemaccessSymbols()
485 if (Reg != AArch64::X0) in EmitHwasanMemaccessSymbols()
487 .addReg(AArch64::X0) in EmitHwasanMemaccessSymbols()
1128 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
1135 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
1142 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
1143 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
DAArch64CollectLOH.cpp261 static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
263 if (AArch64::X0 <= Reg && Reg <= AArch64::X28) in mapRegToGPRIndex()
264 return Reg - AArch64::X0; in mapRegToGPRIndex()
/third_party/skia/src/core/
DSkLineClipper.cpp37 double X0 = src[0].fX; in sect_with_horizontal() local
41 double result = X0 + ((double)Y - Y0) * (X1 - X0) / (Y1 - Y0); in sect_with_horizontal()
46 return (float)pin_unsorted(result, X0, X1); in sect_with_horizontal()
58 double X0 = src[0].fX; in sect_with_vertical() local
62 double result = Y0 + ((double)X - X0) * (Y1 - Y0) / (X1 - X0); in sect_with_vertical()
/third_party/flutter/skia/src/core/
DSkLineClipper.cpp37 double X0 = src[0].fX; in sect_with_horizontal() local
41 double result = X0 + ((double)Y - Y0) * (X1 - X0) / (Y1 - Y0); in sect_with_horizontal()
46 return (float)pin_unsorted(result, X0, X1); in sect_with_horizontal()
58 double X0 = src[0].fX; in sect_with_vertical() local
62 double result = Y0 + ((double)X - X0) * (Y1 - Y0) / (X1 - X0); in sect_with_vertical()
/third_party/cmsis/CMSIS/DSP/Source/FilteringFunctions/
Darm_biquad_cascade_df1_f16.c65 float16_t X0, X1, X2, X3; /* temporary input */ in arm_biquad_cascade_df1_f16() local
89 X0 = *pIn++; in arm_biquad_cascade_df1_f16()
120 accVec = vfmaq(accVec, coeffs, X0); in arm_biquad_cascade_df1_f16()
163 X0 = *pIn++; in arm_biquad_cascade_df1_f16()
194 accVec = vfmaq(accVec, coeffs, X0); in arm_biquad_cascade_df1_f16()
212 Xn1 = X0; in arm_biquad_cascade_df1_f16()
221 Xn2 = X0; in arm_biquad_cascade_df1_f16()
Darm_biquad_cascade_df1_f32.c179 float32_t X0, X1, X2, X3; /* temporary input */ in arm_biquad_cascade_df1_f32() local
202 X0 = *pIn++; in arm_biquad_cascade_df1_f32()
217 accVec = vfmaq(accVec, coeffs, X0); in arm_biquad_cascade_df1_f32()
260 X0 = *pIn++; in arm_biquad_cascade_df1_f32()
275 accVec = vfmaq(accVec, coeffs, X0); in arm_biquad_cascade_df1_f32()
292 Xn1 = X0; in arm_biquad_cascade_df1_f32()
302 Xn2 = X0; in arm_biquad_cascade_df1_f32()
/third_party/skia/modules/skparagraph/gm/
Dsimple_gm.cpp124 const SkScalar X0 = pos[0].fX; in drawFromVisitor() local
125 const SkScalar X1 = X0 + info->advanceX; in drawFromVisitor()
130 SkScalar x0 = X0; in drawFromVisitor()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVAsmBackend.cpp90 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
97 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
103 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc90 AArch64::X0, AArch64::X1
219 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
230 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
233 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
255 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
463 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
474 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
499 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
915 if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
922 if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
[all …]
/third_party/mesa3d/src/amd/addrlib/src/gfx11/
Dgfx11SwizzlePattern.h1782 …{X0, X1, Y0, X2, Y1, Y2, X3, …
1783 …{0, X0, Y0, X1, Y1, X2, Y2, …
1784 …{0, 0, X0, Y0, X1, Y1, X2, …
1785 …{0, 0, 0, X0, Y0, X1, X2, …
1786 …{0, 0, 0, 0, X0, Y0, X1, …
1787 …{S0, X0, Y0, X1, Y1, X2, Y2, …
1788 …{0, S0, X0, Y0, X1, Y1, X2, …
1789 …{0, 0, S0, X0, Y0, X1, Y1, …
1790 …{0, 0, 0, S0, X0, Y0, X1, …
1791 …{0, 0, 0, 0, S0, X0, Y0, …
[all …]
/third_party/mbedtls/tests/suites/
Dtest_suite_mpi.function564 mbedtls_mpi X, Y, X0, Y0;
566 mbedtls_mpi_init( &X0 ); mbedtls_mpi_init( &Y0 );
568 TEST_ASSERT( mbedtls_test_read_mpi( &X0, 16, X_hex ) == 0 );
578 TEST_ASSERT( mbedtls_mpi_cmp_mpi( &Y, &X0 ) == 0 );
589 TEST_ASSERT( mbedtls_mpi_cmp_mpi( &Y, &X0 ) == 0 );
599 TEST_ASSERT( mbedtls_mpi_cmp_mpi( &X, &X0 ) == 0 );
604 mbedtls_mpi_free( &X0 ); mbedtls_mpi_free( &Y0 );
611 mbedtls_mpi X, X0;
612 mbedtls_mpi_init( &X ); mbedtls_mpi_init( &X0 );
615 TEST_ASSERT( mbedtls_test_read_mpi( &X0, 16, X_hex ) == 0 );
[all …]

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