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/third_party/mesa3d/src/intel/tools/tests/gen6/
Dasr.asm1 asr(8) g11<1>D g11<4>D 16D { align16 1Q };
2 asr(8) g2<1>D g2<8,8,1>D 16D { align1 1Q };
3 asr(16) g2<1>D g2<8,8,1>D 16D { align1 1H };
4 asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q };
5 asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H };
6 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
7 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
8 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
9 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
10 asr(8) g26<1>D g25<4>D g20<4>UD { align16 1Q };
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen7.5/
Dasr.asm1 asr(8) g13<1>.xD g5.4<0>.zD g5.4<0>.wUD { align16 1Q };
2 asr(8) g57<1>.xD g38<4>.xD 0x00000001UD { align16 1Q };
3 asr(8) g3<1>D g2<0,1,0>D g2.1<0,1,0>UD { align1 1Q };
4 asr(16) g3<1>D g2<0,1,0>D g2.1<0,1,0>UD { align1 1H };
5 asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q };
6 asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H };
7 asr(8) g4<1>.xD g14<4>.xD 0x00000010UD { align16 NoDDClr 1Q };
8 asr(8) g4<1>.yD g1<0>.xD 0x00000010UD { align16 NoDDChk 1Q };
9 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
10 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
[all …]
/third_party/ffmpeg/libavcodec/arm/
Dsimple_idct_armv6.S66 pkhtb r2, ip, r10,asr #16 /* r3 = W7 | (W3 << 16) */
105 pkhtb r2, ip, r10,asr #16 /* r3 = W7 | (W3 << 16) */
135 mov r4, r3, asr #\shift
136 mov r8, r2, asr #\shift
140 mov r5, r3, asr #\shift
141 mov r9, r2, asr #\shift
145 mov r6, r3, asr #\shift
146 mov r10,r2, asr #\shift
150 mov r7, r3, asr #\shift
151 mov r11,r2, asr #\shift
[all …]
Dsimple_idct_armv5te.S152 add v2, v1, a4, asr #16
155 add v1, v1, a4, asr #16
263 mov ip, ip, asr #20
271 mov a4, a4, asr #20
281 mov ip, ip, asr #20
289 mov a4, a4, asr #20
299 mov ip, ip, asr #20
307 mov a4, a4, asr #20
317 mov ip, ip, asr #20
325 mov a4, a4, asr #20
[all …]
Dflacdsp_arm.S35 add_sh r2, r2, r4, asr r3
38 add_sh lr, lr, r4, asr r3
46 add_sh r2, r2, r4, asr r3
67 add_sh r6, r6, r4, asr r3
69 add_sh r7, r7, r5, asr r3
79 add_sh r5, r5, r4, asr r3
123 add_sh r6, r6, r4, asr r3
125 add_sh r7, r7, r5, asr r3
143 add_sh r5, r5, r4, asr r3
Djrevdct_arm.S140 mov r8, r8, asr #11
146 mov r8, r8, asr #11
152 mov r8, r8, asr #11
158 mov r8, r8, asr #11
164 mov r8, r8, asr #11
170 mov r8, r8, asr #11
176 mov r8, r8, asr #11
182 mov r8, r8, asr #11
279 mov r8, r8, asr #18
285 mov r8, r8, asr #18
[all …]
Dvp8dsp_armv6.S93 pkhtb r6, r8, r6, asr #16 @ dc{0,1}[1]
95 pkhtb r12, r2, r12, asr #16 @ dc{2,3}[1]
99 pkhtb r7, r9, r7, asr #16 @ dc{0,1}[3]
101 pkhtb lr, r3, lr, asr #16 @ dc{2,3}[3]
131 asr r6, #3 @ block[0][0]
132 asr r12, #3 @ block[0][1]
133 asr r1, #3 @ block[0][2]
134 asr r10, #3 @ block[0][3]
138 asr r8, r8, #19 @ block[1][0]
140 asr r7, r7, #19 @ block[1][1]
[all …]
Dpixblockdsp_armv6.S36 pkhtb r6, r4, r6, asr #16
38 pkhtb r12, r8, r12, asr #16
64 pkhtb r6, r6, r9, asr #16
71 pkhtb r9, r5, r9, asr #16
Dhevcdsp_idct_neon.S237 asr r1, #1
239 asr r1, #(14 - \bitdepth)
252 asr r1, #1
254 asr r1, #(14 - \bitdepth)
273 asr r1, #1
275 asr r1, #(14 - \bitdepth)
297 asr r1, #1
299 asr r1, #(14 - \bitdepth)
Dac3dsp_armv6.S61 usat r8, #6, r8, asr #5 @ address
62 usat lr, #6, lr, asr #5
75 usat r8, #6, r8, asr #5 @ address
Dsimple_idct_arm.S81 … mov r7, r1, asr #16 @ R7=R1>>16=ROWr16[1] (evaluate it now, as it could be useful later)
101 mov r2, r2, asr #16 @ R2=ROWr16[3]
137 mov r3, r3, asr #16 @ R3=ROWr16[5]
141 mov r4, r4, asr #16 @ R4=ROWr16[7]
242 and r8, r11, r8, asr #ROW_SHIFT @ R8=0x0000FFFF & ((a0+b0)>>11)
249 and r8, r11, r8, asr #ROW_SHIFT @ R8=0x0000FFFF & ((a2+b2)>>11)
256 and r8, r11, r8, asr #ROW_SHIFT @ R8=0x0000FFFF & ((a3-b3)>>11)
263 and r8, r11, r8, asr #ROW_SHIFT @ R8=0x0000FFFF & ((a1-b1)>>11)
432 mov r8, r8, asr #COL_SHIFT
433 mov r9, r9, asr #COL_SHIFT
[all …]
Didctdsp_armv6.S30 pkhtb r5, r5, r4, asr #16
32 pkhtb lr, lr, r12, asr #16
Dsbcdsp_armv6.S63 pkhtb r3, r12, r3, asr #16 @ combine t1[0] and t1[1]
84 pkhtb r12, r14, r12, asr #16 @ combine t1[2] and t1[3]
127 pkhtb r3, r12, r3, asr #16 @ combine t1[6] and t1[7]
149 pkhtb r3, r12, r3, asr #16 @ combine t1[4] and t1[5]
171 pkhtb r3, r12, r3, asr #16 @ combine t1[0] and t1[1]
192 pkhtb r12, r14, r12, asr #16 @ combine t1[2] and t1[3]
Dvp8_armv6.S74 pkhtbne r11, r11, r11, asr #16
123 pkhtb r11, r11, r11, asr #16
142 pkhtb r11, r11, r11, asr #16
/third_party/mesa3d/src/intel/tools/tests/gen7/
Dasr.asm1 asr(8) g13<1>.xD g5.4<0>.zD g5.4<0>.wUD { align16 1Q };
2 asr(8) g57<1>.xD g38<4>.xD 0x00000001UD { align16 1Q };
3 asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q };
4 asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H };
5 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
6 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
7 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
8 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
/third_party/mesa3d/src/intel/tools/tests/gen5/
Dasr.asm1 asr.nz.f0.0(8) null<1>D -g1.6<0,1,0>D 31D { align1 };
2 asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr };
3 asr(8) g4<1>D g5<4>D g4<4>UD { align16 };
4 asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 };
5 asr(8) g5<1>D g3<8,8,1>D 0x00000002UD { align1 };
6 asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr };
/third_party/mesa3d/src/intel/tools/tests/gen8/
Dasr.asm1 asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q };
2 asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H };
3 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
4 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
5 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
6 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
/third_party/mesa3d/src/intel/tools/tests/gen9/
Dasr.asm1 asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q };
2 asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H };
3 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
4 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
5 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
6 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
/third_party/mesa3d/src/intel/tools/tests/gen4/
Dasr.asm1 asr(16) g4<1>D -g1.6<0,1,0>D 31D { align1 compr };
2 asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr };
3 asr(8) g4<1>D g5<4>D g4<4>UD { align16 };
4 asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 };
5 asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr };
/third_party/mesa3d/src/intel/tools/tests/gen4.5/
Dasr.asm1 asr(16) g4<1>D -g1.6<0,1,0>D 31D { align1 compr };
2 asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr };
3 asr(8) g4<1>D g5<4>D g4<4>UD { align16 };
4 asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 };
5 asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr };
/third_party/skia/tools/gpu/
DTestContext.cpp32 auto asr = SkScopeExit(this->onPlatformGetAutoContextRestore()); in makeCurrentAndAutoRestore() local
34 return asr; in makeCurrentAndAutoRestore()
/third_party/flutter/skia/tools/gpu/
DTestContext.cpp41 auto asr = SkScopeExit(this->onPlatformGetAutoContextRestore()); in makeCurrentAndAutoRestore() local
43 return asr; in makeCurrentAndAutoRestore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td443 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
449 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
450 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
463 def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
464 def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h29 asr, enumerator
47 case ARM_AM::asr: return "asr"; in getShiftOpcStr()
59 case ARM_AM::asr: return 2; in getShiftOpcEncoding()
/third_party/ltp/tools/sparse/sparse-src/validation/linear/
Dbug-assign-op0.c1 int asr(int s) in asr() function

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